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Performance comparison of SIMD implementations of the discrete wavelet transform 离散小波变换SIMD实现的性能比较
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.51
A. Shahbahrami, B. Juurlink, S. Vassiliadis
{"title":"Performance comparison of SIMD implementations of the discrete wavelet transform","authors":"A. Shahbahrami, B. Juurlink, S. Vassiliadis","doi":"10.1109/ASAP.2005.51","DOIUrl":"https://doi.org/10.1109/ASAP.2005.51","url":null,"abstract":"This paper focuses on SIMD implementations of the 2D discrete wavelet transform (DWT). The transforms considered are Daubechies' real-to-real method of four coefficients (Daub-4) and the integer-to-integer (5, 3) lifting scheme. Daub-4 is implemented using SSE and the lifting scheme using MMX, and their performance is compared to C implementations on a Pentium 4 processor. The MMX implementation of the lifting scheme is up to 4.0/spl times/ faster than the corresponding C program for a 1-level 2D DWT, while the SSE implementation of Daub-4 is up to 2.6/spl times/ faster than the C version. It is shown that for some image sizes, the performance is significantly hampered by the so called 64K aliasing problem, which occurs in the Pentium 4 when two data blocks are accessed that are a multiple of 64K apart. It is also shown that for the (5, 3) lifting scheme, a 12-bit word size is sufficient for a 5-level decomposition of the 2D DWT for images of up to 10 bits per pixel.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133987684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec 为H.264高级视频编解码器设计并实现了一种高性能、硅效率高的算术编码加速器
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.30
J. Núñez-Yáñez, V. Chouliaras
{"title":"Design and implementation of a high-performance and silicon efficient arithmetic coding accelerator for the H.264 advanced video codec","authors":"J. Núñez-Yáñez, V. Chouliaras","doi":"10.1109/ASAP.2005.30","DOIUrl":"https://doi.org/10.1109/ASAP.2005.30","url":null,"abstract":"A high performance and silicon efficient hardware architecture for binary arithmetic coding (BAC) acceleration is presented and its application to entropy coding in the context of the H.264 video compressor standard described. The proposed hardware architecture remains bit compatible with the software implementation used in the H.264 ITU standard. The renormalization sequence that maintains the state variables in the appropriate range has been rewritten in order to enable a data independent throughput in hardware of 1 symbol per clock cycle. The instruction set extensions required to be implemented as part of the ISA of a controlling RISC are proposed. Finally, ASIC and FPGA implementations are obtained and the performance and complexity compared with recent implementations of the well-known MQ-coder reported.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128717251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Logic models supporting the design of MOBILE-based RTD circuits 支持基于mobile的RTD电路设计的逻辑模型
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.43
M. Avedillo, J. Quintana, H. Pettenghi
{"title":"Logic models supporting the design of MOBILE-based RTD circuits","authors":"M. Avedillo, J. Quintana, H. Pettenghi","doi":"10.1109/ASAP.2005.43","DOIUrl":"https://doi.org/10.1109/ASAP.2005.43","url":null,"abstract":"Threshold logic is a computational model widely used in the design of resonant tunnelling diodes (RTDs) based circuits, i.e. these circuits are built from threshold gates. This paper explores two other computational models, generalized threshold gates (GTG) and multi-threshold threshold gates (MTTGs), also suitable to be realized with mobile based RTD structures. Circuits implementing them are described. Both logic models are generalizations of threshold logic and so the proposed circuit topologies further increase the functionality of the original TGs. Implementations of a non threshold function with the GTG and MTTG topologies are shown and compared.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134632989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Recursive filtering on a vector DSP with linear speedup 线性加速的矢量DSP递归滤波
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.55
M. V. D. Horst, K. V. Berkel, J. Lukkien, R. H. Mak
{"title":"Recursive filtering on a vector DSP with linear speedup","authors":"M. V. D. Horst, K. V. Berkel, J. Lukkien, R. H. Mak","doi":"10.1109/ASAP.2005.55","DOIUrl":"https://doi.org/10.1109/ASAP.2005.55","url":null,"abstract":"Vector DSPs, or SIMD DSPs, have received considerable attention recently, since they are considered to be a viable alternative for dedicated hardware in signal processing for multimedia and wireless communication. It is possible to construct dedicated hardware for IIR filters with a linear speedup, but because of their recursive nature these filters are considered difficult to map efficiently on a vector DSP. The IIR programs for vector DSPs presented so far have their speedup bounded by the order of the filter. In this paper we present a program that has a linear speed up, in the sense that doubling the vector size doubles the throughput. The program is a vectorization of the incremental block-state architecture. The speedup of this program is not bounded by the order of the filter, and even works for low order filters. Besides strided memory access, no special processor features are required by our program. As a proof of concept we implemented it on the Philips EVP processor.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129549692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Power breakdown analysis for a heterogeneous NoC platform running a video application 运行视频应用的异构NoC平台的电源击穿分析
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.52
A. Lambrechts, P. Raghavan, A. Leroy, G. Talavera, T. Aa, M. Jayapala, F. Catthoor, D. Verkest, Geert Deconinck, H. Corporaal, F. Robert, J. Carrabina
{"title":"Power breakdown analysis for a heterogeneous NoC platform running a video application","authors":"A. Lambrechts, P. Raghavan, A. Leroy, G. Talavera, T. Aa, M. Jayapala, F. Catthoor, D. Verkest, Geert Deconinck, H. Corporaal, F. Robert, J. Carrabina","doi":"10.1109/ASAP.2005.52","DOIUrl":"https://doi.org/10.1109/ASAP.2005.52","url":null,"abstract":"Users expect future handheld devices to provide extended multimedia functionality and have long battery life. This type of application imposes heavy constraints on performance and power consumption and forces designers to optimize all parts of their platform. Evaluating the overall platform power breakdown is therefore critical to determine where to spend the efforts on power optimization. Surprisingly, few studies exist on that topic and decisions generally rely on common belief. We have realized a complete power breakdown for a realistic platform to identify the major power bottlenecks. This paper presents this power assessment of a realistic heterogeneous network on chip platform including processors, network and data/instruction memory hierarchy, running a video processing chain from camera to display. Our power breakdown identifies the main bottlenecks in the memory hierarchy and the foreground memory, and shows that global interconnect is not that critical for a well-optimized application mapping.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122366386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Complex fixed-point matrix inversion using transport triggered architecture 利用传输触发结构的复杂不动点矩阵反演
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.25
A. Burian, P. Salmela, J. Takala
{"title":"Complex fixed-point matrix inversion using transport triggered architecture","authors":"A. Burian, P. Salmela, J. Takala","doi":"10.1109/ASAP.2005.25","DOIUrl":"https://doi.org/10.1109/ASAP.2005.25","url":null,"abstract":"Fixed-point simulations for inverting matrices using transport triggered architectures are performed. Several methods are implemented in fixed-point: the Cholesky decomposition as a direct method, Newton iterations as an iterative method, and Strassen Newton algorithm as a combined recursive method. Fixed-point implementations of these matrix inversion algorithms are tested and analyzed. A division-free implementation is targeted.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128251421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reducing interconnection resource overhead in nano-scale FPGAs through MVL signal systems 通过MVL信号系统减少纳米级fpga的互连资源开销
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.56
P. Kelly, T. McGinnity, L. Maguire
{"title":"Reducing interconnection resource overhead in nano-scale FPGAs through MVL signal systems","authors":"P. Kelly, T. McGinnity, L. Maguire","doi":"10.1109/ASAP.2005.56","DOIUrl":"https://doi.org/10.1109/ASAP.2005.56","url":null,"abstract":"In nano-architectures, transistor counts place extreme demands on interconnection resources. The chronic problem of interconnect area versus device area becomes more acute than it currently is. Even with multilayering of conductors there may still be attenuation and propagation delay issues which at the extremes of nano-architecture severely limit performance. When reconfigurable devices such as field programmable gate arrays (FPGAs) are considered the issue of interconnection resources becomes even more acute due to the inherent redundancy already apparent in existing devices. The authors propose the use of a multiple valued signal system to increase functional density whilst reducing the interconnection resource overhead in FPGA based nano-architectures.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128671038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multiply-accumulate architecture for a special class of optimal extension fields 一类特殊的最优扩展域的乘-累加结构
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.46
M. O. Sanu, E. Swartzlander
{"title":"Multiply-accumulate architecture for a special class of optimal extension fields","authors":"M. O. Sanu, E. Swartzlander","doi":"10.1109/ASAP.2005.46","DOIUrl":"https://doi.org/10.1109/ASAP.2005.46","url":null,"abstract":"Finite field arithmetic is useful in the implementation of error-correcting codes as well as cryptographic protocols. Large finite field numbers are particularly important in the implementation of elliptic curve cryptography. This paper presents a multiply-accumulate architecture for multipliers over a special class of type II optimal extension fields (OEFs). Type II OEFs are Galois fields GF (p/sup m/) with p a pseudo-Mersenne prime of the form p = 2/sup n/ $c, where c is \"small\", and an irreducible binomial of the form f (z) = z/sup m/ $2 exists over GF (p). The Type II OEF multiplier presented uses merged arithmetic to combine multiple multiply and addition operations together. Unlike previous work, the multiplier also performs subfield and extension field reduction in parallel for this class of finite fields. Though the multiplier design requires large silicon area for practical implementation, it obviates the need for performing subfield and extension field reduction separately, thereby reducing the overall delay.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121135115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Instruction set customization of application specific processors for network processing: a case study 用于网络处理的特定应用程序处理器的指令集定制:一个案例研究
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.41
M. Mozumdar, K. Karuri, A. Chattopadhyay, S. Kraemer, H. Scharwächter, H. Meyr, G. Ascheid, R. Leupers
{"title":"Instruction set customization of application specific processors for network processing: a case study","authors":"M. Mozumdar, K. Karuri, A. Chattopadhyay, S. Kraemer, H. Scharwächter, H. Meyr, G. Ascheid, R. Leupers","doi":"10.1109/ASAP.2005.41","DOIUrl":"https://doi.org/10.1109/ASAP.2005.41","url":null,"abstract":"The growth of the Internet in the last decade has made current networking applications immensely complex. Systems running such applications need special architectural support to meet the tight constraints of power and performance. This paper presents a case study of architecture exploration and optimization of an application specific instruction set processor (ASIP) for networking applications. The case study particularly focuses on the effects of instruction set customization for applications from different layers of the protocol stack. Using a state-of-the-art VLIW processor as the starting template, and architecture description language (ADL) based architecture exploration tools, this case study suggests possible instruction set and architectural modifications that can speed-up some networking applications up to 6.8 times. Moreover, this paper also shows that there exist very few similarities between diverse networking applications. Our results suggest that, it is extremely difficult to have a common set of architectural features for efficient network protocol processing and, ASIPs with specialized instruction sets can become viable solutions for such an application domain.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"88 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116303129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A parallel automaton string matching with pre-hashing and root-indexing techniques for content filtering coprocessor 具有预哈希和根索引技术的并行自动字符串匹配的内容过滤协处理器
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.8
Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Y. Lai
{"title":"A parallel automaton string matching with pre-hashing and root-indexing techniques for content filtering coprocessor","authors":"Kuo-Kun Tseng, Ying-Dar Lin, Tsern-Huei Lee, Y. Lai","doi":"10.1109/ASAP.2005.8","DOIUrl":"https://doi.org/10.1109/ASAP.2005.8","url":null,"abstract":"We propose a new parallel automaton string matching approach and its hardware architecture for content filtering coprocessor. This new approach can improve the average matching time of the parallel automaton with pre-hashing and root-indexing techniques. The pre-hashing technique uses a hashing function to verify quickly the text against the partial patterns in the automaton, and the root-indexing technique matches multiple bytes for the root state in one single matching. A popular automaton algorithm, Aho-Corasick (AC) is chosen to be implemented by adding the two techniques; we employ these two techniques in a memory efficient version of AC namely bitmap AC. For the average-case time, our approach improves bitmap AC by 494% and 224% speedup for URL and virus patterns, respectively. Since pre-hashing and root-indexing techniques can be concurrently executed with bitmap AC in the hardware, our proposed approach has the same worst-case time as bitmap AC.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117259042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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