2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)最新文献_第3页

CONAN - a design exploration framework for reliable nano-electronics architectures 可靠的纳米电子结构的设计探索框架

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.26

S. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, A. Rubio

{"title":"CONAN - a design exploration framework for reliable nano-electronics architectures","authors":"S. Cotofana, A. Schmid, Y. Leblebici, A. Ionescu, O. Soffke, P. Zipf, M. Glesner, A. Rubio","doi":"10.1109/ASAP.2005.26","DOIUrl":"https://doi.org/10.1109/ASAP.2005.26","url":null,"abstract":"In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our approach is a generic (parametrical) architectural template. Configurable nanostructures for reliable nano electronics (CONAN), which embeds support for reliability at various levels of abstractions. Some of the main reliability sources are regular and decentralized structures based on simple basic computation cells designed to be robust against disturbances and noise, fault tolerance based on hardware, time and information redundancy applied at the basic cell level as well as at higher levels, self diagnosis assisted by the dynamic reconfiguration of basic computation cells and interconnect rerouting. Within the CONAN template, both technology dependent and independent models co-exists such that the more abstract layers are technology independent while the lower levels can be retargeted to various fabrication technologies. Our proposal is application-oriented and allows the designers to deal with unpredictability, and low reliability, which are unavoidable characteristics of future emerging nano-devices. When combined with the underlying software, the tools supporting the CONAN approach allow the designer to check whether the design constraints are fulfilled before performing a detailed implementation and provides means to trade area, delay, and power consumptions for reliability. As such, this proposal is a call-to-arms to mobilize the efforts of systems designers in order to achieve a systematic design methodology for reliable systems.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124044464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Analytical approach to massively parallel architectures for nanotechnologies 纳米技术大规模并行架构的分析方法

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.14

Björn Jäger, Jörg-Christian Niemann, U. Rückert

{"title":"Analytical approach to massively parallel architectures for nanotechnologies","authors":"Björn Jäger, Jörg-Christian Niemann, U. Rückert","doi":"10.1109/ASAP.2005.14","DOIUrl":"https://doi.org/10.1109/ASAP.2005.14","url":null,"abstract":"In the emerging field of single-chip multiprocessors (CMP), analytical models of performance and power consumption are necessary for design space exploration and the analysis of existing architectures. In the light of ever decreasing structure sizes in microchips the scalability of proposed CMPs is of great interest to the developers. Looking even further into the future at the possibilities offered by, e. g., nanotechnology, a set of such models may help to identify promising architectures and possible bottlenecks even before the enabling technologies exist. In this paper, we present our current work in this area in the form of two models. The first and very basic model is based on Amdahl's law and gives a first promising outlook on chip multiprocessing. Based on the more complex BSP model, our second model takes the on-chip communication into account and thus allows a much more detailed look at the architecture. In both cases, basic laws of circuit technology have been combined with the underlying models that now take the effects of device scaling into account. Later, we also present the GigaNetIC architecture, a CMP developed by our research group. It was then analyzed by applying the BSP-based model.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129804702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

On the advantages of serial architectures for low-power reliable computations 论串行体系结构在低功耗可靠计算中的优势

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.48

Valeriu Beiu, S. Aunet, J. Nyathi, R. R. Rydberg, A. Djupdal

{"title":"On the advantages of serial architectures for low-power reliable computations","authors":"Valeriu Beiu, S. Aunet, J. Nyathi, R. R. Rydberg, A. Djupdal","doi":"10.1109/ASAP.2005.48","DOIUrl":"https://doi.org/10.1109/ASAP.2005.48","url":null,"abstract":"This paper explores low power reliable micro-architectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (V/sub th/). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180nm, 120 nm, and 70nm) identify the supply voltages where the power-delay and energy-delay products are minimized. These show that redundant serial adders are not only low power and reliable, but can trade speed for power in a wide range (by varying V/sub DD/ both above and below V/sub th/).","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130959210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Using TLM for exploring bus-based SoC communication architectures 使用TLM探索基于总线的SoC通信架构

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.65

S. Pasricha, M. Ben-Romdhane

{"title":"Using TLM for exploring bus-based SoC communication architectures","authors":"S. Pasricha, M. Ben-Romdhane","doi":"10.1109/ASAP.2005.65","DOIUrl":"https://doi.org/10.1109/ASAP.2005.65","url":null,"abstract":"As billion transistor system-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design requirements in shrinking time-to-market windows, and have begun using an IP-based SoC design methodology that permits reuse of key SoC functional components. Since the communication architectures connecting components in these SoC designs significantly impact system performance, it is imperative that designers explore the communication design space efficiently, quickly and early in the design flow. Transaction level modeling (TLM) is an emerging abstraction that facilitates early exploration of SoC architectures. This paper outlines a typical IP-based SoC design flow, and presents the cycle count accurate at transaction boundaries (CCATB) modeling abstraction which is a fast, efficient and flexible approach for exploring bus-based communication architectures in SoC designs. The CCATB models not only take less time to model but are also faster to simulate than existing modeling abstractions for communication architecture exploration such as pin-accurate BCA (PA-BCA) and transaction based BCA (T-BCA). Experimental results on several industrial SoC subsystem case studies show that CCATB models are faster than PA-BCA by as much as 120% on average and by 67% on average when compared to T-BCA, demonstrating the advantages of CCATB-based TLM abstraction for exploring bus-based SoC communication architectures.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Customising application-specific multiprocessor systems: a case study 定制特定于应用程序的多处理器系统:一个案例研究

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.28

A. Fidjeland, W. Luk

引用次数: 3

A programmable DSP architecture for wireless communication systems 用于无线通信系统的可编程DSP体系结构

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.9

A. Kamalizad, N. Tabrizi, N. Bagherzadeh, Akira Hatanaka

{"title":"A programmable DSP architecture for wireless communication systems","authors":"A. Kamalizad, N. Tabrizi, N. Bagherzadeh, Akira Hatanaka","doi":"10.1109/ASAP.2005.9","DOIUrl":"https://doi.org/10.1109/ASAP.2005.9","url":null,"abstract":"Programmable solutions for fast mobile communication systems are attracting ever-growing attention due to different and also evolving communication standards. They overcome the shortcomings of ASIC design, by allowing multimode operation, and general-purpose processors by exploiting the inherent data level parallelism in the application. MaRS, a macro-pipelined reconfigurable system, is a domain specific programmable parallel DSP architecture, aimed at harnessing the inherent parallelism in such applications. In this paper, we present the MaRS architecture along with the latest modifications and algorithms that are mapped onto it. We have mapped an IEEE 802.11a WLAN transmitter including a parallel FFT and soft decision Viterbi decoder on MaRS. Our simulation results show that the performance achieved on MaRS meets the stringent timing constraints of the IEEE 802.11a baseband transceiver at its highest rate, with 20% slack, leaving a playground for system level power optimization. Finally, we have mapped the EEMBC telecom suite on MaRS to evaluate and compare our architecture with existing architectures.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121559466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Architectural extensions for elliptic curve cryptography over GF(2/sup m/) on 8-bit microprocessors 8位微处理器上GF(2/sup m/)上椭圆曲线加密的架构扩展

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.15

H. Eberle, A. Wander, N. Gura, S. C. Shantz, Vipul Gupta

引用次数: 46

Zippy - a coarse-grained reconfigurable array with support for hardware virtualization Zippy——支持硬件虚拟化的粗粒度可重构数组

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.69

Christian Plessl, M. Platzner

引用次数: 35

The midlifekicker microarchitecture evaluation metric 中年杀手微架构评估指标

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.62

S. Vassiliadis, L. Sousa, G. Gaydadjiev

引用次数: 5

Artificial deadlock detection in process networks for ECLIPSE ECLIPSE进程网络中的人工死锁检测

2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.18

N. Bharath, N. Bussa

{"title":"Artificial deadlock detection in process networks for ECLIPSE","authors":"N. Bharath, N. Bussa","doi":"10.1109/ASAP.2005.18","DOIUrl":"https://doi.org/10.1109/ASAP.2005.18","url":null,"abstract":"Kahn process network (KPN) is a popular model of computation for describing streaming applications. In a KPN model, processes communicate through unbounded unidirectional FIFOs. When theoretically unbounded FIFOs are implemented using finite memory, artificial deadlocks can occur due to one or more FIFOs having insufficient sizes. Generally, a system designer must be able to make a design time trade-off between execution time and memory usage, preferably using no more memory than required for obtaining a certain execution time. But it is practically impossible to decide at design time, FIFO sizes that are sufficient to run the application without any artificial deadlocks. Hence, there is a need for runtime mechanism for handling the artificial deadlock situations in process networks. Existing mechanisms detect artificial deadlocks only after all KPN processes block. This results in excessive blocking of processes and an application that appears to hang. In this paper, we present an improved mechanism for early detection of artificial deadlocks and its implementation on ECLIPSE (extended CPU local irregular processing architecture), an application domain specific architecture.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126227491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6