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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)最新文献

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Architectural support for accelerating congestion control applications in network processors 在网络处理器中加速拥塞控制应用程序的架构支持
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.16
Byeong Kil Lee, L. John, E. John
{"title":"Architectural support for accelerating congestion control applications in network processors","authors":"Byeong Kil Lee, L. John, E. John","doi":"10.1109/ASAP.2005.16","DOIUrl":"https://doi.org/10.1109/ASAP.2005.16","url":null,"abstract":"Complex network protocols and various network services require significant processing capability for modern intelligent network applications. One of the significant features in modern networks is differentiated service. Along with differentiated service, rapidly changing network environments result in congestion problems. In this paper, we analyze the characteristics of representative congestion control applications - scheduling and queue management algorithms, and we propose application-specific acceleration technique using ILP (instruction level parallelism) and PLP (packet level parallelism). From the ILP perspective, new instruction set extensions for fast conditional operations are applied for congestion control applications. Based on our experiments, proposed architectural extensions show 10-12% improvement in performance for instruction set enhancements. For PLP, we propose a hardware acceleration model based on detailed analysis of congestion control applications. In order to get large throughputs, large number of processing elements and a parallel comparator are designed. Such hardware accelerators provide large parallelism proportional to the number of processing elements added. As the performance of general purpose processors rapidly increases, defining architectural extensions (e.g., MMX as in multimedia applications) for general purpose processors could be an alternative solution for wide range of network applications.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122740856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Table-based polynomials for fast hardware function evaluation 基于表的多项式快速硬件功能评估
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.61
J. Detrey, F. D. Dinechin
{"title":"Table-based polynomials for fast hardware function evaluation","authors":"J. Detrey, F. D. Dinechin","doi":"10.1109/ASAP.2005.61","DOIUrl":"https://doi.org/10.1109/ASAP.2005.61","url":null,"abstract":"Many general table-based methods for the evaluation in hardware of elementary functions have been published. The bipartite and multipartite methods implement a first-order approximation of the function using only table lookups and additions. Recently, a single multiplier second order method of similar inspiration has also been published. This paper extends such methods to approximations of arbitrary order, using adders, small multipliers, and very small ad hoc powering units. We obtain implementations that are both smaller and faster than previously published approaches. This paper also deals with the FPGA implementation of such methods. Previous work have consistently shown that increasing the approximation degree lead to not only smaller but also faster designs, as the reduction of the table size meant a reduction of its lookup time, which compensated for the addition and multiplication time. The experiments in this paper suggest that this still holds when going from order 2 to order 3, but no longer when using higher order approximations, where a tradeoff appears.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121610180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 93
On estimations for compiling software to FPGA-based systems 基于fpga系统的软件编译估计
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.47
João MP Cardoso
{"title":"On estimations for compiling software to FPGA-based systems","authors":"João MP Cardoso","doi":"10.1109/ASAP.2005.47","DOIUrl":"https://doi.org/10.1109/ASAP.2005.47","url":null,"abstract":"This paper presents recent advances in a compiler infrastructure to map algorithms described in a Java subset to FPGA-based platforms. We explain how delays and resources are estimated to guide the compiler through scheduling and temporal partitioning. The compiler supports complex analytical models to estimate resources and delays for each functional unit. The paper presents experimental results for a number of benchmarks. Those results also arise a question when performing temporal partitioning: shall we try to group as many computational structures in the same configuration or shall we have several configurations?.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Hardware/software interface for multi-dimensional processor arrays 多维处理器阵列的硬件/软件接口
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.38
A. Darte, Steven Derrien, T. Risset
{"title":"Hardware/software interface for multi-dimensional processor arrays","authors":"A. Darte, Steven Derrien, T. Risset","doi":"10.1109/ASAP.2005.38","DOIUrl":"https://doi.org/10.1109/ASAP.2005.38","url":null,"abstract":"On most recent systems on chip, the performance bottleneck is the on-chip communication medium, bus or network. Multimedia applications require a large communication bandwidth between the processor and graphic hardware accelerators, hence an efficient communication scheme using burst mode is mandatory. In the context of data-flow hardware accelerators, we approach this problem as a classical resource-constrained problem. We explain how to use recent optimization techniques so as to define a conflict-free schedule of input/output for multi-dimensional processor arrays (e.g. 2D grids). This schedule is static and allows us to perform further optimizations such as grouping successive data in packets to operate in burst mode. We also present an effective VHDL implementation on FPGA and compare our approach to a run-time congestion resolution showing important gains in hardware area.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134063996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Via-aware global routing for good VLSI manufacturability and high yield 通过感知全局路由良好的超大规模集成电路制造能力和高良率
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.67
Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qiming Zhu, Xiaodong Hu, G. Yan
{"title":"Via-aware global routing for good VLSI manufacturability and high yield","authors":"Yang Yang, Tong Jing, Xianlong Hong, Yu Hu, Qiming Zhu, Xiaodong Hu, G. Yan","doi":"10.1109/ASAP.2005.67","DOIUrl":"https://doi.org/10.1109/ASAP.2005.67","url":null,"abstract":"CAD tools have become more and more important for integrated circuit (IC) design since a complicated system can be designed into a single chip, called system-on-a-chip (SOC), in which physical design tool is an essential and critical part. We try to consider the via minimization problem as early as possible in physical design. We propose a routing method focusing on minimizing vias while considering mutability and wire-length constraint. That is, in the global routing phase, we minimize the number of bends, which is closely related to the number of vias. Previous work only dealt with very small nets, but our algorithm is general for the nets with any size. Experimental results show that our algorithm can greatly reduce the count of bends for various sizes of nets while meeting the constraints of congestion and wire-length.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133819686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Automated instruction-set extension of embedded processors with application to MPEG-4 video encoding 嵌入式处理器的自动指令集扩展，应用于MPEG-4视频编码
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.20
N. Kavvadias, S. Nikolaidis
{"title":"Automated instruction-set extension of embedded processors with application to MPEG-4 video encoding","authors":"N. Kavvadias, S. Nikolaidis","doi":"10.1109/ASAP.2005.20","DOIUrl":"https://doi.org/10.1109/ASAP.2005.20","url":null,"abstract":"A recent approach to platform-based design involves the use of extensible processors, offering architecture customization possibilities. Part of the designer responsibilities is the domain-specific extension of the baseline processor to fit customer requirements. Key issues of this process are the automated application analysis and candidate instruction identification/selection for implementation as application-specific functional units (AFUs). In this paper, a design approach that encapsulates automated workload characterization and instruction generation is utilized for extending processors to efficiently support embedded application sets. The method used for instruction generation is a highly parameterized adaptation of the MaxMISO technique, which allows for fast design space exploration. It is proven that only a small number of AFUs are needed in order to support the algorithms of interest (MPEG-4 encoding kernels) and that it is possible to achieve 2/spl times/ to 3.5/spl times/ performance improvements although further possibilities such as subword parallelization are not currently regarded.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"32 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120821255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Instruction set architecture enhancements for video processing 视频处理的指令集架构增强
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.40
J. V. D. Waerdt, S. Vassiliadis
{"title":"Instruction set architecture enhancements for video processing","authors":"J. V. D. Waerdt, S. Vassiliadis","doi":"10.1109/ASAP.2005.40","DOIUrl":"https://doi.org/10.1109/ASAP.2005.40","url":null,"abstract":"This paper presents some of the enhancements to the TriMedia instruction set architecture (ISA), as supported by the TM3270 media-processor. We show how the new operations are used to optimize the individual MPEG2 encoder kernels. Furthermore, we quantify the contribution of these kernels to overall MPEG2 encoder performance. We introduce two-slot operations, collapsed load operations with interpolations, and new multiplication operations. The encoder's texture pipeline for a bi-directionally predicted 8/spl times/8 block is performed in 358 VLIW instructions. MPEG2 encoding at CIF resolution at 25 frames per second is achieved within 33.5 MHz of processor performance.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124616408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware 加速从划分关键软件部件到粗粒度可重构硬件
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.60
M. D. Galanis, G. Dimitroulakos, C. Goutis
{"title":"Speedups from partitioning critical software parts to coarse-grain reconfigurable hardware","authors":"M. D. Galanis, G. Dimitroulakos, C. Goutis","doi":"10.1109/ASAP.2005.60","DOIUrl":"https://doi.org/10.1109/ASAP.2005.60","url":null,"abstract":"In this paper, we propose a hardware/software partitioning method for improving applications' performance in embedded systems. Critical software parts are accelerated on hardware of a single-chip generic system comprised by an embedded processor and coarse-grain reconfigurable hardware. The reconfigurable hardware is realized by a 2D array of processing elements. The partitioning flow utilizes an analysis procedure at the basic-block level for detecting kernels in software. A list-based mapping algorithm has been developed for estimating the execution cycles of kernels on coarse-grain reconfigurable arrays. The proposed partitioning flow has been largely automated for a program description in C language. Extensive hardware/software experiments on five real-life applications are presented. It is shown that the benchmarks spend an average of 69% of their instruction count in 11% on average of their code that correspond to the kernels' code. The results illustrate that by mapping critical code on coarse-grain reconfigurable hardware, speedups ranging from 1.2 to 3.7, with an average value of 2.2, are achieved.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127054006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
On-chip lookup tables for fast symmetric-key encryption 片上查找表用于快速对称密钥加密
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.49
A. M. Fiskiran, R. Lee
{"title":"On-chip lookup tables for fast symmetric-key encryption","authors":"A. M. Fiskiran, R. Lee","doi":"10.1109/ASAP.2005.49","DOIUrl":"https://doi.org/10.1109/ASAP.2005.49","url":null,"abstract":"On public communication networks such as the Internet, data confidentiality can be provided by symmetric key ciphers. One of the most common operations used in symmetric key ciphers are table lookups. These frequently constitute the largest fraction of the execution time when the ciphers are implemented using a typical RISC-like instruction set. To accelerate these table lookups, we describe a new hardware module, called PTLU (for parallel table lookup), which consists of multiple lookup tables that can be accessed in parallel. A novel combinational circuit included in the module can optionally perform simple logic operations on the data read from the tables. On a single issue 64-bit RISC processor, PTLU provides maximum speedups of 7.7x for AES and 5.4x for DES. With wordsize scaling, PTLU speedups are significantly higher than that available through more conventional architectural techniques such as superscalar or VUW execution.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125623262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x 小型FPGA多项式近似与3位系数和低精度估计的幂x
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.59
R. Michard, A. Tisserand, Nicolas Veyrat-Charvillon
{"title":"Small FPGA polynomial approximations with 3-bit coefficients and low-precision estimations of the powers of x","authors":"R. Michard, A. Tisserand, Nicolas Veyrat-Charvillon","doi":"10.1109/ASAP.2005.59","DOIUrl":"https://doi.org/10.1109/ASAP.2005.59","url":null,"abstract":"This paper presents small FPGA implementations of low precision polynomial approximations of functions without multipliers. Our method uses degree-2 or degree-3 polynomial approximations with at most 3-bit coefficients and low-precision estimations of the powers of x. Here we denote by 3-bit coefficients values with at most 3 nonzero and possibly noncontiguous signed bits (e.g., 1.0010001~). This leads to very small operators by replacing the costly multipliers by a small number of additions. Our method provides approximations with very low average error and is suitable for signal processing applications.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134164041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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