{"title":"Side-channel aware design: algorithms and architectures for elliptic curve cryptography over GF(2/sup n/)","authors":"L. Batina, N. Mentens, B. Preneel, I. Verbauwhede","doi":"10.1109/ASAP.2005.57","DOIUrl":"https://doi.org/10.1109/ASAP.2005.57","url":null,"abstract":"This paper proposes efficient algorithms for elliptic curve cryptography (ECC). As an example a compact and efficient FPGA architecture for ECC over finite fields of even characteristic is presented. The implementation is balanced in order to increase the security w.r.t. simple side channel attacks.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127893977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"CASPER: an integrated energy-driven approach for task graph scheduling on distributed embedded systems","authors":"V. Kianzad, S. Bhattacharyya, G. Qu","doi":"10.1109/ASAP.2005.23","DOIUrl":"https://doi.org/10.1109/ASAP.2005.23","url":null,"abstract":"For multiprocessor embedded systems, the dynamic voltage scaling (DVS) technique can be applied to scheduled applications for energy reduction. DVS utilizes slack in the schedule to slow down processes and save energy. Therefore, it is generally believed that the maximal energy saving is achieved on a schedule with the minimum makespan (maximal slack). Most current approaches treat task assignment, scheduling, and DVS separately. In this paper, we present a framework called CASPER (combined assignment, scheduling, and power-management) that challenges this common belief by integrating task scheduling and DVS under a single iterative optimization loop via genetic algorithm. We have conducted extensive experiments to validate the energy efficiency of CASPER. For homogeneous multiprocessor systems (in which all processors are of the same type), we consider a recently proposed slack distribution algorithm (PDP-SPM) by S. Hua and G. Qu (2005): applying PDP-SPM on the schedule with the minimal makespan gives an average of 53.8% energy saving; CASPER finds schedules with slightly larger makespan but a 57.3% energy saving, a 7.8% improvement. For heterogeneous systems, we consider the power variation DVS (PV-DVS) algorithm by Schmitz et al. (2004), CASPER improves its energy efficiency by 8.2%. Finally, our results also show that the proposed single loop CASPER framework saves 23.3% more energy over GMA+EE-GLSA by Schmitz et al. (2002), the only other known integrated approach with a nested loop that combines scheduling and power management in the inner loop but leaves assignment in the outer loop.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Simple 4-bit processor based on quantum-dot cellular automata (QCA)","authors":"K. Waluś, M. Mazur, G. Schulhof, G. Jullien","doi":"10.1109/ASAP.2005.58","DOIUrl":"https://doi.org/10.1109/ASAP.2005.58","url":null,"abstract":"We describe the design and layout of a simple 4-bit processor based on quantum dot cellular automata (QCA) using the QCADesigner design tool. The processor design is based on an accumulator architecture which reduces the required hardware complexity and allows for reasonable simulation times. Our aim is to provide evidence that QCA has potential applications in future computers provided that the underlying technology is made feasible.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131867740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploring design space of VLIW architectures","authors":"G. Ascia, V. Catania, M. Palesi, Davide Patti","doi":"10.1109/ASAP.2005.33","DOIUrl":"https://doi.org/10.1109/ASAP.2005.33","url":null,"abstract":"Architectures based on very long instruction word (VLIW) have found fertile ground in multimedia electronic appliances thanks to their ability to exploit high degrees of instruction level parallelism (ILP) with a reasonable tradeoff in complexity and silicon costs. Effective compiler support for predicated execution using the hyperblock, drastically increases the ILP even for control-dominated applications in which the branch instruction frequency is very high. The use of these techniques, however, is known to increase the instruction footprint, consequently putting pressure on the memory hierarchy. In this paper, we evaluate the performance/power trade-off in a system comprising a VLIW processor and a two-level hierarchical memory subsystem. Via simulation, we show that the efficiency of a compiler that is able to exploit predicate execution by hyperblock formation is greatly affected by the configuration of the memory subsystem as well as the configurable processor parameters. The enabling or disabling of hyperblock formation should therefore not be evaluated separately or independently, but seen as a further free parameter to be tuned in a strategy of design space exploration.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134090358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Steiner, P. Chan, L. Imbert, G. Jullien, V. Dimitrov, G. McGibney
{"title":"A fault-tolerant modulus replication complex FIR filter","authors":"I. Steiner, P. Chan, L. Imbert, G. Jullien, V. Dimitrov, G. McGibney","doi":"10.1109/ASAP.2005.6","DOIUrl":"https://doi.org/10.1109/ASAP.2005.6","url":null,"abstract":"In this paper we propose an architecture for the implementation of fault-tolerant computation for a high throughput multirate equalizer used in a 1 Gbps asymmetrical wireless LAN. Exploiting the algebraic structure of the modulus replication residue number system (MRRNS) minimizes the area overhead, and the area cost to correct a fault in a single computational channel is 82.7%. Generalized results for single error correction showing significant area savings are also presented.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Casablanca II: implementation of a real-time RISC core for embedded systems","authors":"Kiyofumi Tanaka","doi":"10.1109/ASAP.2005.22","DOIUrl":"https://doi.org/10.1109/ASAP.2005.22","url":null,"abstract":"We extended general-purpose RISC processor architecture and developed a new RISC core, Casablanca II, for supporting real-time processing in embedded systems. The processor core has multiple register-sets and achieves fast context-switching by automatically changing the active register-set and reducing overheads to save and restore the contents of the registers when exceptions or interruptions occur. In addition, the core has mechanisms for explicit data cache control, enabling data prefetching and fast DMA, which is invoked by executing extended instructions. In this paper, we describe the organization of Casablanca II developed by using an ASIC process and present preliminary evaluation of the processor.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"29 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Behavioral specification of control interface for signal processing applications","authors":"J. Lemaitre, Sylvain Alliot, E. Deprettere","doi":"10.1109/ASAP.2005.21","DOIUrl":"https://doi.org/10.1109/ASAP.2005.21","url":null,"abstract":"Data-driven applications that are mapped onto large-scale systems need to be controlled for (re-)configuration, test and monitoring. Such systems consist of distributed and heterogeneous components. We specify the behavior of a control network independent of the system architecture and independent of the data-driven application. We address particularly the key problem of the interfacing between the control model and the data-driven application model.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127369403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using symbolic feasibility tests during design space exploration of heterogeneous multi-processor systems","authors":"T. Schlichter, C. Haubelt, Frank Hannig, J. Teich","doi":"10.1109/ASAP.2005.64","DOIUrl":"https://doi.org/10.1109/ASAP.2005.64","url":null,"abstract":"The task of automatic design space exploration of heterogeneous multi-processor systems is often tackled with evolutionary algorithms. In this paper, we propose a novel approach in combining evolutionary algorithms with symbolic techniques in order to improve the convergence speed. The main idea is to guide the search towards the feasible region by utilizing symbolic techniques. We present experimental results showing the advantages of our novel approach, especially when the search space contains only few feasible solutions, what is often the case when designing heterogeneous multi-processor systems.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125986565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Toyokazu Akiyama, Tatsuya Akutsu, M. Aritsugi, Benjamin Bustos Budiarto, W. Castelnovo, Yabing Chen, Susumu Date, W. Fan, Kazutoshi Fujikawa, Jack Fu, K. Harumoto, Bin He, Gísli R. Hjaltason, D. Hu, Tianming Hu, Yan Huang, Arvind Hulgeri, Naoki Ishibashi, Y. Ishikawa, Min Jian, Panos Kalnis, J. Kamahara, A. Kayed, Dao Dinh Kha, Zoé Lacroix, Charley Li, Chengkai Li, Han-Li Li, Xue Li, Yingjiu Li, Yao Liu, Y. Liu, Daofeng Luo, N. Mamoulis, Maude Manouvrier, M. Mesiti, G. Mihaila, Jun Miyazaki, Kenichi Mori, M. Nakano, Andrea Nucita, Makoto Onizuka, T. Pedersen, Alex Pongpech, Iko Pramudiono, Weining Qian, Jong-Won Roh, S. Sadiq, Qiongmao Shen, I. Stanoi, Changyi Su, Sam Sung, Takayuki Tamura, Yufei Tao, T. Terada, H. Toh, M. Toyoda, Yong Shun Tzeng, Haixun Wang, Jin Wang, Xiaoyu Wang, Yu Wang, M. Wawryniuk, Liangwei Yang, Naofumi Yoshida, K. Yura, Jun Zhang, Zhen Zhang
{"title":"External Referees","authors":"Toyokazu Akiyama, Tatsuya Akutsu, M. Aritsugi, Benjamin Bustos Budiarto, W. Castelnovo, Yabing Chen, Susumu Date, W. Fan, Kazutoshi Fujikawa, Jack Fu, K. Harumoto, Bin He, Gísli R. Hjaltason, D. Hu, Tianming Hu, Yan Huang, Arvind Hulgeri, Naoki Ishibashi, Y. Ishikawa, Min Jian, Panos Kalnis, J. Kamahara, A. Kayed, Dao Dinh Kha, Zoé Lacroix, Charley Li, Chengkai Li, Han-Li Li, Xue Li, Yingjiu Li, Yao Liu, Y. Liu, Daofeng Luo, N. Mamoulis, Maude Manouvrier, M. Mesiti, G. Mihaila, Jun Miyazaki, Kenichi Mori, M. Nakano, Andrea Nucita, Makoto Onizuka, T. Pedersen, Alex Pongpech, Iko Pramudiono, Weining Qian, Jong-Won Roh, S. Sadiq, Qiongmao Shen, I. Stanoi, Changyi Su, Sam Sung, Takayuki Tamura, Yufei Tao, T. Terada, H. Toh, M. Toyoda, Yong Shun Tzeng, Haixun Wang, Jin Wang, Xiaoyu Wang, Yu Wang, M. Wawryniuk, Liangwei Yang, Naofumi Yoshida, K. Yura, Jun Zhang, Zhen Zhang","doi":"10.1109/TIME.2005.23","DOIUrl":"https://doi.org/10.1109/TIME.2005.23","url":null,"abstract":"Kinh Nguyen Hideo Nakata Jing Li Alena Griffiths Jitian Xiao Hsian-Chou Liao Taizo Kojima P au1 Taylor Shengke Yu Ji-Tzay Yang Kuo-Chan Huang Chong-Hua Hu Jiun-Liang Chen Yanchun Zhang Sanjay Kumar Madiria Bin-Shiang Liang A. Fuller Steve Atkinson Chung-Bin Yan Ming-Feng Chen Damien Watkins Michael Kolling Christopher Exton Shihong Chen Wei Ge Jian Lu Huaimin Wang Shixian Li Aoying Zhou Haolin Sheng Fenxiao Wang Hong Zhao Hong Mei Suqin Zhang Shuo Bai Baisu Huang Jinpeng Huai Chao Liu Tao Huang Mingchun Zheng Weidu Jiang Jiguo Yang Bing Zhu Dajun Yang Xiaoqun Chen Wanghong Yuan Qiong Wu Yuanhong Wang Hongbiao Zhao Benhe Guo Qingping Tan Jiazhong Zhang Jieshi Cai Bo Yi Chunqi Shi Dianxiang Xu Daoxu Chen Dehua Ju Lizhu Zhou Guogui Yang Zhiying Zhou Linxi Cai Qiangshu Yang Hong Ning Jianmin Xiao Bin Zhou Shangteng Huang Li Zhou Hongjun He Linpeng Huang Jiangning Liu Qing Shen Sikun Li Dingyi Wu Shiyou Wang Chuan Xie Tianyi Zang Xiaodong Liu Shouren Hu Ji Wang Dianxi Shi","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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