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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)最新文献

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Decimal floating-point square root using Newton-Raphson iteration 十进制浮点平方根使用牛顿-拉夫森迭代
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.29
Liang-Kai Wang, M. Schulte
{"title":"Decimal floating-point square root using Newton-Raphson iteration","authors":"Liang-Kai Wang, M. Schulte","doi":"10.1109/ASAP.2005.29","DOIUrl":"https://doi.org/10.1109/ASAP.2005.29","url":null,"abstract":"With continued reductions in feature size, additional functionality may be added to future microprocessors to boost the performance of important application domains. Due to growth in commercial, financial, and Internet-based applications, decimal floating point arithmetic is now attracting more attention and hardware support for decimal operations is being considered by various computer manufacturers. In order to standardize decimal number formats and operations, specifications for decimal floating point arithmetic have been added to the draft revision of the IEEE-754 standard for floating point arithmetic (IEEE-754R). This paper presents an efficient arithmetic algorithm and hardware design for decimal floating point square root. This design uses an optimized piecewise linear approximation, a modified Newton-Raphson iteration, a specialized rounding technique, and a modified decimal multiplier. Synthesis results show that a 64-bit (16 digit) implementation of decimal square root, which is compliant with IEEE-754R, has an estimated critical path delay of 0.95 ns and a maximum latency of 210 clock cycles when implemented using a sequential multiplier and LSI Logic's 0.11 micron Gflx-P standard cell library.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127914095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A low-power processor architecture optimized for wireless devices 一种针对无线设备优化的低功耗处理器架构
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.7
A. Efthymiou, J. Garside, I. Papaefstathiou
{"title":"A low-power processor architecture optimized for wireless devices","authors":"A. Efthymiou, J. Garside, I. Papaefstathiou","doi":"10.1109/ASAP.2005.7","DOIUrl":"https://doi.org/10.1109/ASAP.2005.7","url":null,"abstract":"The advantages of power-aware processors are well known. This paper presents an innovative processor architecture optimized for wireless environments. The presented architecture incorporates a certain power-aware microarchitectural technique, called pipeline depth adaptation and it is tailored to self-timed processors. With this technique, a processor is able to alter its pipeline depth, while in operation, trading speed and energy use. The pipeline depth is changed by making selected pipeline registers transparent. A shallow pipeline has lower energy consumption for two reasons: the capacitance driven by the load signal of the 'collapsed' pipeline registers is not switched and the reduction in branch latency and data-dependent stalls reduce the cycles per instruction (CPI) of the processor. An analysis of the advantages of using pipeline depth adaptation in an asynchronous processor is given, supported by simulation results based on a real asynchronous processor and on applications that are frequently executed on a wireless environment. Finally, a method of dynamically adapting the pipeline depth is described and evaluated which only reduces the pipeline depth when a branch instruction is expected. The presented architecture has a relatively lower power consumption than a conventional similar architecture, therefore it can be useful in wireless environments.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127233487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Generating efficient custom FPGA soft-cores for control-dominated applications 为控制主导应用生成高效的定制FPGA软核
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.37
L. L'Hours
{"title":"Generating efficient custom FPGA soft-cores for control-dominated applications","authors":"L. L'Hours","doi":"10.1109/ASAP.2005.37","DOIUrl":"https://doi.org/10.1109/ASAP.2005.37","url":null,"abstract":"In this paper, we present an automated flow geared toward the synthesis of application specific micro-controllers for FPGAs, targeted at control dominated applications. Our flow takes as input an application described in C, and uses profiling information to extract a specialized instruction set. This instruction set is then mapped to a generic RISC micro-architecture model, for which we generate a synthesizable VHDL description, along with its associated program. The flow has been validated on a set of representative applications and our preliminary experimental results show that our generated architectures are very competitive with FPGA vendor specific processor soft-cores, in terms of code size, resource usage and performance.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133305967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Virtual hierarchical design representations for distributed optimization of multi-million gate designs 数百万门设计分布式优化的虚拟分层设计表示
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.68
Thi Nguyen, K. Shi
{"title":"Virtual hierarchical design representations for distributed optimization of multi-million gate designs","authors":"Thi Nguyen, K. Shi","doi":"10.1109/ASAP.2005.68","DOIUrl":"https://doi.org/10.1109/ASAP.2005.68","url":null,"abstract":"A virtual hierarchical design optimization method has been developed to combine strength of the flat and the hierarchical optimization methods for efficient and quality optimization of multi-million gate designs in a distributed computing environment. A novel design representation \"virtual hierarchy\" is proposed for sub-design optimization in a distributed computing environment. The principle and the implementation details of the method are described. The method has been successfully applied to a number of designs.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"68 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114454161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-line multioperand addition based on on-line full adders 基于在线全加法器的在线多操作数加法
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.50
J. Villalba, J. Hormigo, J. Prades, E. Zapata
{"title":"On-line multioperand addition based on on-line full adders","authors":"J. Villalba, J. Hormigo, J. Prades, E. Zapata","doi":"10.1109/ASAP.2005.50","DOIUrl":"https://doi.org/10.1109/ASAP.2005.50","url":null,"abstract":"In this paper we deal with the online addition of multioperands for conventional, carry save (CS) and/or signed-digit (SD) numbers. We propose an online full adder (olFA) as the key element to design trees of adders to deal with multioperands. We also consider mixed inputs (e.g. SD and CS) and how to obtain the output in any of these representations. We show that for dealing with online multioperands it is more efficient to work with online CS trees based on olFAs than with online SD tree based on online SD adders. Finally a novel olFA-based architecture is proposed to directly deal with SD numbers.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115053574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Communication-centric SoC design for nanoscale domain 纳米级领域以通信为中心的SoC设计
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.24
Ümit Y. Ogras, Jingcao Hu, R. Marculescu
{"title":"Communication-centric SoC design for nanoscale domain","authors":"Ümit Y. Ogras, Jingcao Hu, R. Marculescu","doi":"10.1109/ASAP.2005.24","DOIUrl":"https://doi.org/10.1109/ASAP.2005.24","url":null,"abstract":"In the realm of 35nm technology, it becomes possible to have thousands of IP blocks that need to communicate efficiently. Large-scale integration of these blocks onto a single chip makes the use of truly scalable networks-on-chips (NoC) communication architectures inevitable. This paper provides an overview of the outstanding research issues involved in designing application-specific NoC architectures by considering explicitly the level of customization envisioned in the communication architecture. For each category of approaches, we discuss the significance of the problem, provide a problem statement and survey the relevant solutions to date.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125095217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Eliminating sorting in IP lookup devices using partitioned table 使用分区表消除IP查找设备中的排序
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.32
E. Ng, Gyungho Lee
{"title":"Eliminating sorting in IP lookup devices using partitioned table","authors":"E. Ng, Gyungho Lee","doi":"10.1109/ASAP.2005.32","DOIUrl":"https://doi.org/10.1109/ASAP.2005.32","url":null,"abstract":"We present a solution to eliminate the requirements of routing table sorting by prefix length in IP lookup devices using ternary content addressable memories (TCAMs). This reduces delays arising from routing table updates from linear to constant time. This solution introduces slight modifications to the organization of the routing table including the elimination of the built-in priority encoder. The routing table entries are split by output port to remove their dependence on length. Overall, the solution presented reduces the insertion problem to lookup speed while maintaining similar clock rates and storage requirements of traditional designs.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125269892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Design of a hardware accelerator for density based clustering applications 基于密度的集群应用硬件加速器的设计
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.31
J. Pisharath, A. Choudhary
{"title":"Design of a hardware accelerator for density based clustering applications","authors":"J. Pisharath, A. Choudhary","doi":"10.1109/ASAP.2005.31","DOIUrl":"https://doi.org/10.1109/ASAP.2005.31","url":null,"abstract":"Data mining is beginning to be widely used in various application fields. Density based clustering algorithms perform data mining by grouping high-density regions of points to form clusters. In recent years, the data sizes and the problem complexity of this algorithm have increased significantly leading to slower execution of the applications. Faster engines that perform the application tasks quickly and efficiently are the need of the hour. In this paper, we propose a hardware accelerator for density based clustering applications. This accelerator improves the execution speed of the core kernels of this application, which include density calculation and the migration of points to denser regions. We show that this accelerator when integrated with general purpose processors, speed up the kernel execution times by at least 300X.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123163265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An image processor for digital film 用于数字胶片的图像处理器
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.13
Amilcar do Carmo Lucas, R. Ernst
{"title":"An image processor for digital film","authors":"Amilcar do Carmo Lucas, R. Ernst","doi":"10.1109/ASAP.2005.13","DOIUrl":"https://doi.org/10.1109/ASAP.2005.13","url":null,"abstract":"This paper presents an FPGA based hardware architecture, named FlexWAFE, for high resolution, high troughput real-time digital film processing. Complex algorithms require several hundred arithmetic operations per pixel which is beyond the scope of current DSP processors. To simplify programming and yet achieve high clock rates, the architecture combines component configuration with weak programmability. It alleviates the memory bottleneck by an efficient use of internal memory blocks and a multi-stream SDRAM memory scheduler with tightly bounded latency. Several examples of a discrete wavelet transform and a complex noise reducer demonstrate the architecture efficiency.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122859750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Faults, error bounds and reliability of nanoelectronic circuits 纳米电子电路的故障、误差边界和可靠性
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.36
Jie Han, E. Taylor, Jianbo Gao, J. Fortes
{"title":"Faults, error bounds and reliability of nanoelectronic circuits","authors":"Jie Han, E. Taylor, Jianbo Gao, J. Fortes","doi":"10.1109/ASAP.2005.36","DOIUrl":"https://doi.org/10.1109/ASAP.2005.36","url":null,"abstract":"This paper is concerned with faults, error bounds and reliability modeling of nanotechnology-based circuits. First, we briefly review failure mechanisms and fault models in nanoelectronics. Second, reliability functions based on probabilistic models are developed for unreliable logic gates. We then show that fundamental gate error bounds for general probabilistic computation can be derived using the nonlinear mapping functions constructed from the gate models. Finally, an analytical approach is proposed for estimating reliabilities of nanoelectronic circuits. This approach is based on the probabilistic modeling of unreliable logic gates and interconnects. In spite of the approximations used in probabilistic modeling, our study suggests that the proposed approach provides a simple and efficient way to model the reliability of nanoelectronic circuits.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128603521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
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