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2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)最新文献

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Expression synthesis in process networks generated by LAURA LAURA生成过程网络中的表达合成
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.34
Claudiu Zissulescu, B. Kienhuis, E. Deprettere
{"title":"Expression synthesis in process networks generated by LAURA","authors":"Claudiu Zissulescu, B. Kienhuis, E. Deprettere","doi":"10.1109/ASAP.2005.34","DOIUrl":"https://doi.org/10.1109/ASAP.2005.34","url":null,"abstract":"The COMPAAN/LAURA (Stefanov et al., 2004) tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application as a process network in which the control is parameterized and distributed. This control is given as parameterized polytopes that are expressed in terms of pseudo-linear expressions. These expressions cannot always be mapped efficiently onto hardware as they contain multiplication and integer division operations. This obstructs the data flow through the processes. Therefore, we present in this paper the expression compiler that efficiently maps pseudo-linear expressions onto a dedicated hardware data-path in such a way that the distributed and parameterized control never obstructs the data flow through processors. This compiler employs techniques like number theory axioms, method of difference, and predicated static single assignment code.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121452704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Towards a framework for system-level design of multiprocessor SoC platforms for media processing 面向媒体处理的多处理器SoC平台的系统级设计框架
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.63
S. Chakraborty
{"title":"Towards a framework for system-level design of multiprocessor SoC platforms for media processing","authors":"S. Chakraborty","doi":"10.1109/ASAP.2005.63","DOIUrl":"https://doi.org/10.1109/ASAP.2005.63","url":null,"abstract":"Recently, a number of event-centric models have been proposed for analyzing multimedia applications running on multiprocessor system-on-chip (SoC) platforms. This has given shape to a general framework using which different timing and performance analysis questions can be answered in a single coherent manner. Central to this framework is a model for expressing the timing properties associated with different multimedia streams and a means for computing how these properties change as a stream gets successively processed by the different processors of a platform. In contrast to standard event models like periodic or sporadic, this model can accurately capture the data-dependent execution time variabilities associated multimedia tasks and the burstiness of on-chip traffic resulting from multimedia processing. In this paper, we give a high-level view of this framework, describe setups which currently can be modelled using it, and identify possible directions in which this framework should be extended to make it more usable.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131153788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A SW/configware codesign methodology for control dominated applications 一种用于控制主导应用程序的软件/配置软件协同设计方法
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.10
K. B. Chehida, M. Auguin
{"title":"A SW/configware codesign methodology for control dominated applications","authors":"K. B. Chehida, M. Auguin","doi":"10.1109/ASAP.2005.10","DOIUrl":"https://doi.org/10.1109/ASAP.2005.10","url":null,"abstract":"In this paper, we present a partitioning methodology targeting a dynamically reconfigurable architecture. We first identify this class of architectures and point out the lack of underlying tools and compiler support exploiting, with these architectures, the potential task level parallelism (TLP). The applications in today's and the future embedded systems are more and more control dominated making necessary the use of a specification that handles jointly treatment and control. Our methodology starts from a system level specification in safe state machines (SSM: the graphical formalism of ESTEREL) integrating task level granularity treatments (as C function calls) in a control flow environment. After simulation and formal proof, we explicitly partition all the different configurations of the SSM i.e. the different combinations of control and treatment that the system has to perform at each operational tick. We also develop a technique that enables to contain the explosion of the number of these configurations and establish the efficiency of our method through its application to a video supervision application and to the JPEG 2000 standard.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129750390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Instruction set extensions for Reed-Solomon encoding and decoding 里德-所罗门编码和解码的指令集扩展
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.42
S. Mamidi, M. Schulte, D. Iancu, A. Iancu, J. Glossner
{"title":"Instruction set extensions for Reed-Solomon encoding and decoding","authors":"S. Mamidi, M. Schulte, D. Iancu, A. Iancu, J. Glossner","doi":"10.1109/ASAP.2005.42","DOIUrl":"https://doi.org/10.1109/ASAP.2005.42","url":null,"abstract":"Reed-Solomon codes are an important class of error correcting codes used in many applications related to communications and digital storage. The fundamental operations in Reed-Solomon encoding and decoding involve Galois field arithmetic which is not directly supported in general purpose processors. On the other hand, pure hardware implementations of Reed-Solomon coders are not programmable. In this paper, we present a novel algorithm to perform Reed-Solomon encoding. We also propose four new instructions for Galois field arithmetic. We show that by using the instructions, we can speedup Reed-Solomon decoding by a factor of 12 compared to a pure software approach, while still maintaining programmability.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124813454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Real-time H/W implementation of the approximate discrete Radon transform 近似离散Radon变换的实时H/W实现
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.54
Michael T. Frederick, N. VanderHorn, Arun Kumar Somani
{"title":"Real-time H/W implementation of the approximate discrete Radon transform","authors":"Michael T. Frederick, N. VanderHorn, Arun Kumar Somani","doi":"10.1109/ASAP.2005.54","DOIUrl":"https://doi.org/10.1109/ASAP.2005.54","url":null,"abstract":"The Radon transform (RT) is a widely studied algorithm used to perform image pattern extraction in fields such as computer graphics, medical imagery, and avionics. Real time implementation of the discrete RT (DRT) is extremely difficult due to its use of complex trigonometric functions and O(N/sup 3/) time complexity, making its use in video applications difficult. A O(N/sup 2/lgN) approximate discrete (ADRT) has been presented in literature (Brady, 1998) that allows highly parallel computation. This paper presents an architecture that uses the ADRT to create a computation architecture known as the xADRT. Performance analysis indicates that it can achieve a refresh rate of 10 frames per second for use in real time image processing applications.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127954648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
High radix addition via conditional charge transport in single electron tunneling technology 单电子隧穿技术中条件电荷输运的高基数加法
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.39
C. Meenderinck, S. Cotofana, C. Lageweg
{"title":"High radix addition via conditional charge transport in single electron tunneling technology","authors":"C. Meenderinck, S. Cotofana, C. Lageweg","doi":"10.1109/ASAP.2005.39","DOIUrl":"https://doi.org/10.1109/ASAP.2005.39","url":null,"abstract":"This paper investigates the implementation of high radix addition based on the electron counting logic design style in single electron tunneling (SET) technology. A previous proposal for such an adder assumed the presence of a conditional charge movement (MCke) block which was only described as a black box. First, this paper proposes two possible MCke block implementations, each of which is described in detail and validated by means of simulation. Second, one of the proposed MCke implementations is utilized in the design of a 6-bit radix-8 adder. The resulting adder circuit is verified by simulation and evaluation indicated that it requires 187 circuit elements, has a delay of 4.15 ns (assuming an error probability P/sub error/ and a consumed energy of 224 meV).","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114331197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays 缓解了粗粒度可重构阵列的数据内存带宽瓶颈
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.12
G. Dimitroulakos, M. D. Galanis, C. Goutis
{"title":"Alleviating the data memory bandwidth bottleneck in coarse-grained reconfigurable arrays","authors":"G. Dimitroulakos, M. D. Galanis, C. Goutis","doi":"10.1109/ASAP.2005.12","DOIUrl":"https://doi.org/10.1109/ASAP.2005.12","url":null,"abstract":"It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a limited access bandwidth, the applications performance cannot be that high as the multiprocessor system capabilities promise. This is the case for the 2D coarse-grained reconfigurable arrays for which a mapping methodology that aims in improving the mapped applications' performance by alleviating the data bandwidth bottleneck, is presented in this paper. This is achieved by exploiting the applications' data reuse opportunities both at the data dependence and source code level and the architecture's foreground memory. The methodology considers a realistic 2D coarse-grained reconfigurable architecture template, which can model the majority of the existing coarse-grained reconfigurable array architectures. The experimental results show a significant reduction in both execution time and memory accesses for two architecture scenarios that has been achieved by the application of the proposed methodology on a representative set of DSP applications.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116302858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
256-state rate 1/2 Viterbi decoder on TTA processor TTA处理器上的256状态速率1/2维特比解码器
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.5
P. Salmela, Tuomas Järvinen, Teemu Sipilä, J. Takala
{"title":"256-state rate 1/2 Viterbi decoder on TTA processor","authors":"P. Salmela, Tuomas Järvinen, Teemu Sipilä, J. Takala","doi":"10.1109/ASAP.2005.5","DOIUrl":"https://doi.org/10.1109/ASAP.2005.5","url":null,"abstract":"Efficient and flexible Viterbi decoding is an important problem in implementation of modern telecommunications systems. In this paper, a 256-state, rate 1/2 Viterbi decoder is implemented on a transport triggered architecture processor. Due to the processor-based platform, the implementation is flexible and it can achieve relatively high decoding speed. The decoder is implemented by tailoring the processor to meet the requirements of Viterbi decoding. The processor is enhanced with a number of special function units, which accelerate the decoding. As a result, the decoding can be carried out efficiently on a processor-based platform.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126832067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A thread and data-parallel MPEG-4 video encoder for a system-on-chip multiprocessor 用于片上系统多处理器的线程和数据并行MPEG-4视频编码器
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.11
T. Jacobs, J. Núñez-Yáñez
{"title":"A thread and data-parallel MPEG-4 video encoder for a system-on-chip multiprocessor","authors":"T. Jacobs, J. Núñez-Yáñez","doi":"10.1109/ASAP.2005.11","DOIUrl":"https://doi.org/10.1109/ASAP.2005.11","url":null,"abstract":"We studied the dynamic instruction count reduction for a single-thread, vectorized and a multithreaded, nonvectorized, MPEG-4 video encoder. Results indicate a maximum improvement of the order of 88% for 22 CPU contexts for the multithreaded case whereas the single-thread, vectorized version demonstrates an 85% improvement for a vector register file length of 24 bytes, over the scalar case. We present VLSI macrocells of a vector accelerator implementing a subset of the MPEG-4 vector ISA and a 2-way, parametric, bus-based, cache coherent, SoC multiprocessor.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131396971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Variable radix real and complex digit-recurrence division 变基数实数和复数递归除法
2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05) Pub Date : 2005-07-23 DOI: 10.1109/ASAP.2005.66
M. Ercegovac, J. Muller
{"title":"Variable radix real and complex digit-recurrence division","authors":"M. Ercegovac, J. Muller","doi":"10.1109/ASAP.2005.66","DOIUrl":"https://doi.org/10.1109/ASAP.2005.66","url":null,"abstract":"We propose a digit recurrence algorithm for division in real and complex number domains using a variable radix. The objective of the approach is to simplify the prescaling of the operands by using a suitable low radix, and switch to higher radices in the remaining iterations to reduce their number. The prescaling is used to allow a simple quotient digit selection by rounding of the residual. We discuss the algorithm, its implementation, and estimate its time and cost characteristics with respect to fixed high radix division algorithms.","PeriodicalId":412171,"journal":{"name":"2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129689466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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