2012 25th International Conference on VLSI Design最新文献_第3页

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis 可逆逻辑合成中的最小成本容错加法器电路

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.93

Sajib Kumar Mitra, A. Chowdhury

引用次数: 49

A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip 面向特定应用的三维片上网络的TSV串行感知综合框架

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.82

S. Pasricha

{"title":"A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip","authors":"S. Pasricha","doi":"10.1109/VLSID.2012.82","DOIUrl":"https://doi.org/10.1109/VLSID.2012.82","url":null,"abstract":"With increasing performance-per-watt implementation requirements for emerging applications and barriers in interconnect scaling for ultra-deep sub micron (UDSM) technologies, traditional 2D integrated circuits (2D-ICs) are being pushed to their limit. Three dimensional integrated circuits (3D-ICs) have recently emerged as a promising solution that can overcome many of the performance, area, and power concerns in 2D-ICs. In this paper we propose a novel framework (MORPHEUS) for the synthesis of application-specific 3D networks on chip (NoCs). The goal is to generate 3D NoCs that meet application performance constraints while minimizing power dissipation. MORPHEUS incorporates thermal-aware core layout, 3D topology and route generation, and placement of network interfaces (NIs), routers, and serialized vertical through silicon vias (TSVs). Experimental studies on several chip multiprocessor (CMP) applications indicate that our generated solutions notably reduce power dissipation (up to 2.3×) and average latency (up to 1.2×) over 2D NoCs. Comparisons with a previous work on application-specific 3D NoC synthesis also show improvements in power dissipation (up to 1.9×) and average latency (up to 1.6×).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114345434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs 基于低功耗自重构多路复用器的自适应分辨率闪存adc解码器

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.84

C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas

引用次数: 22

A 110-dB Dynamic Range, 76-dB Peak SNR Companding Continuous-Time ?S Modulator for Audio Applications 一个110 db动态范围，76 db峰值信噪比压缩音频应用连续时间调制器

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.45

Saravana Kumar, S. Chatterjee

引用次数: 2

3-D Parasitic Modeling for Rotary Interconnects 旋转互连的三维寄生建模

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.60

V. Honkote, A. More, B. Taskin

引用次数: 8

A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip 数字微流控生物芯片引脚分配与液滴路径协同优化的启发式方法

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.75

R. Mukherjee, H. Rahaman, I. Banerjee, T. Samanta, P. Dasgupta

引用次数: 11

Embedded Tutorial ET2: Digital Subscriber Line 嵌入式教程ET2:数字用户线路

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.41

M. K. K. Rao, V. ShanthaKumariP., B. Sellappan

{"title":"Embedded Tutorial ET2: Digital Subscriber Line","authors":"M. K. K. Rao, V. ShanthaKumariP., B. Sellappan","doi":"10.1109/VLSID.2012.41","DOIUrl":"https://doi.org/10.1109/VLSID.2012.41","url":null,"abstract":"Digital Subscriber Line (DSL) is a family of standards that allow existing twisted pair copper lines to carry modulated digital signals which uses telephone network and unused frequency Spectrum. In this tutorial we describe DSL (Digital Subscriber Line), comparing with POTS and ISDN. We explain the different DSL flavors available with the modulation techniques used and also discuss challenges in getting high performance and throughput, achieving xDSL rate and meeting the DSL standard. We begin by introducing DSL having a pair of modems CO (Central office) and CPE (Customer Premises Equipment) and talk about frequency spectrums. We explain the limitations of POTS (Plain Old Telephone System) with Dial-up Connection and ISDN (Integrated Services Digital Network), and advantages of DSL over POTS. Next we describe various flavors of DSL with their frequency spectrums, power enhancements, standardization, profiles, and band plans. We discuss different modulation techniques with their advantages and disadvantages, including Single carrier Modulation like CAP and QAM and Multi Carrier Modulation like DMT. We explain the interferers/noise: Line Attenuation, The channel attenuation, Bridged taps, Impulse noise, White noise, NEXT, FEXT, RE Interference. We conclude the tutorial with a description of full activation and initialization phases. The targeted audience for the tutorial is designers, developers, testers, people working in the area of VDSL, ADSL technology and People working on different platforms like DSLAM's, Central office, Customer premises equipment, Gateway products as well as products related to access network who are familiar with copper line and modems.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126228679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

GPU Implementation of a Programmable Turbo Decoder for Software Defined Radio Applications 用于软件无线电应用的可编程Turbo解码器的GPU实现

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.62

Dhiraj Reddy Nallapa Yoge, N. Chandrachoodan

引用次数: 25

HD Resolution Intra Prediction Architecture for H.264 Decoder H.264解码器的高清分辨率帧内预测架构

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.55

Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese

引用次数: 0

Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology 用响应面法精确估计FinFET标准电池的泄漏

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.77

S. Chaudhuri, Prateek Mishra, N. Jha

{"title":"Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology","authors":"S. Chaudhuri, Prateek Mishra, N. Jha","doi":"10.1109/VLSID.2012.77","DOIUrl":"https://doi.org/10.1109/VLSID.2012.77","url":null,"abstract":"Among different multi-gate transistors, Fin FETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current in Fin FET standard cells under the effect of variations in gate length (LG), fin thickness (TSI), gate-oxide thickness (TOX) and gate-work function (ΦG). To the best of our knowledge, this is the first attempt to develop analytical models for leakage estimation of Fin FET devices/logic gates based on TCAD simulations of adjusted 2D device cross-sections that have been shown to track TCAD simulations of 3D device behavior within a 1-3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage models for different logic styles, e.g., shorted-gate (SG) and independent-gate (IG) Fin FETs, at the 22nm technology node. The leakage estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results obtained for different adjusted-2D (3D) devices/logic gates with a maximum root mean square error (RMSE) of 5.28% (7.03%).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120938921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17