2012 25th International Conference on VLSI Design最新文献_第2页

Intra-Task Dynamic Cache Reconfiguration 任务内动态缓存重构

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.109

Hadi Hajimiri, P. Mishra

引用次数: 14

SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation 基于侧通道分析的后硅验证逆向工程

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.88

Xinmu Wang, S. Narasimhan, A. Krishna, S. Bhunia

{"title":"SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation","authors":"Xinmu Wang, S. Narasimhan, A. Krishna, S. Bhunia","doi":"10.1109/VLSID.2012.88","DOIUrl":"https://doi.org/10.1109/VLSID.2012.88","url":null,"abstract":"Reverse Engineering (RE) has been historically considered as a powerful approach to understand electronic hardware in order to gain competitive intelligence or accomplish piracy. In recent years, it has also been looked at as a way to authenticate hardware intellectual properties in the court of law. In this paper, we propose a beneficial role of RE in post-silicon validation of integrated circuits (IC) with respect to IC functionality, reliability and integrity. Unlike traditional destructive RE approaches, we propose a fast non-destructive side-channel analysis approach that can hierarchically extract structural information from an IC through its transient current signature. Such a top-down side-channel analysis approach is capable of reliably identifying pipeline stages and functional blocks. It is also suitable to distinguish sequential elements from combinational gates. For extraction of random logic structures (e.g. control blocks and finite state machines) we combine side-channel analysis with logic testing based Boolean function extraction. The proposed approach is amenable to automation, scalable, and can be applied as part of post-silicon validation process to verify that each IC implements exclusively the functionality described in the specification and is free from malicious modification or Trojan attacks. Simulation results on a pipelined DLX processor demonstrate the effectiveness of the proposed approach.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130892187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Power Aware Hardware Prototyping of Multiclass SVM Classifier Through Reconfiguration 基于重构的多类SVM分类器功耗感知硬件原型

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.47

R. A. Patil, G. Gupta, V. Sahula, A. S. Mandal

引用次数: 23

Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management 基于dvs的动态热管理中最佳性能点的运行时间预测

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.63

Junyoung Park, H. M. Ustun, J. Abraham

{"title":"Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management","authors":"Junyoung Park, H. M. Ustun, J. Abraham","doi":"10.1109/VLSID.2012.63","DOIUrl":"https://doi.org/10.1109/VLSID.2012.63","url":null,"abstract":"Due to the increasing trend toward greater processor power density and computationally intensive applications, Dynamic Thermal Management (DTM) has become an essential technique in modern processors. Among many DTM techniques, Dynamic Voltage Scaling (DVS) is widely used because of its chief virtue - a cubic reduction in power at the relatively minor cost of a linear performance penalty. Because this reduction comes at a cost in execution speed, a key point of DVS-based DTM research is how accurately the processor predicts the optimal performance point where it can meet the thermal constraints while also minimizing the performance penalty. In this paper, we propose a new DVS-based DTM technique that makes the prediction of the optimal performance point more accurate. To achieve this, run-time prediction techniques are used and different power compositions due to process variations are considered from a VLSI perspective. The prediction process is performed by referring to one of the Look-Up Tables (LUTs) prepared during design time and also the average clock enable ratio that is dynamically calculated at run time. The simulation results show that we can achieve maximum processor performance while keeping the processor temperature from exceeding the threshold temperature.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121462486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands 基于多电压岛的三维片上网络综合的电力输送网络感知框架

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.81

N. Kapadia, S. Pasricha

{"title":"A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands","authors":"N. Kapadia, S. Pasricha","doi":"10.1109/VLSID.2012.81","DOIUrl":"https://doi.org/10.1109/VLSID.2012.81","url":null,"abstract":"IR drops in a Power Delivery Network (PDN) on chip multi-processors (CMPs) can worsen the quality of voltage supply and thereby affect overall performance. This problem is more severe in 3D CMPs with network-on-chip (NoC) fabrics where the current in the PDN increases proportionally to the number of device layers. Even though the PDN and NoC design goals are non-overlapping, both the optimizations are interdependent, for instance, each new core mapping on the 3D die will change traffic patterns and have a unique distribution of IR-drops in the PDN. Unfortunately, designers today seldom consider design of PDN while synthesizing NoCs. If NoC synthesis is carried out without considering the associated PDN design cost, it can easily result in an overall sub-optimal design. In this work, for the first time, we propose a novel PDN-aware 3D NoC synthesis framework that minimizes NoC power while meeting performance goals, and optimizes the corresponding PDN for total number of Voltage Regulator Modules (VRMs), current efficiency, and grid-wire width while satisfying IR-drop constraints. Our experimental results show that the proposed methodology provides more comprehensive results compared to a traditional approach where the NoC synthesis step does not consider the PDN costs.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122588791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip 面向特定应用的三维片上网络的TSV串行感知综合框架

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.82

S. Pasricha

{"title":"A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip","authors":"S. Pasricha","doi":"10.1109/VLSID.2012.82","DOIUrl":"https://doi.org/10.1109/VLSID.2012.82","url":null,"abstract":"With increasing performance-per-watt implementation requirements for emerging applications and barriers in interconnect scaling for ultra-deep sub micron (UDSM) technologies, traditional 2D integrated circuits (2D-ICs) are being pushed to their limit. Three dimensional integrated circuits (3D-ICs) have recently emerged as a promising solution that can overcome many of the performance, area, and power concerns in 2D-ICs. In this paper we propose a novel framework (MORPHEUS) for the synthesis of application-specific 3D networks on chip (NoCs). The goal is to generate 3D NoCs that meet application performance constraints while minimizing power dissipation. MORPHEUS incorporates thermal-aware core layout, 3D topology and route generation, and placement of network interfaces (NIs), routers, and serialized vertical through silicon vias (TSVs). Experimental studies on several chip multiprocessor (CMP) applications indicate that our generated solutions notably reduce power dissipation (up to 2.3×) and average latency (up to 1.2×) over 2D NoCs. Comparisons with a previous work on application-specific 3D NoC synthesis also show improvements in power dissipation (up to 1.9×) and average latency (up to 1.6×).","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114345434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Minimum Cost Fault Tolerant Adder Circuits in Reversible Logic Synthesis 可逆逻辑合成中的最小成本容错加法器电路

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.93

Sajib Kumar Mitra, A. Chowdhury

引用次数: 49

A Library for Passive Online Verification of Analog and Mixed-Signal Circuits 模拟和混合信号电路无源在线验证库

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.98

D. Pal, P. Dasgupta, S. Mukhopadhyay

引用次数: 0

Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs 基于低功耗自重构多路复用器的自适应分辨率闪存adc解码器

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.84

C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas

引用次数: 22

Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future 教程2:可逆逻辑:超低功耗，故障测试和新兴纳米技术的基础和应用，以及未来的挑战

2012 25th International Conference on VLSI Design Pub Date : 2012-01-07 DOI: 10.1109/VLSID.2012.29

H. Thapliyal, N. Ranganathan

{"title":"Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future","authors":"H. Thapliyal, N. Ranganathan","doi":"10.1109/VLSID.2012.29","DOIUrl":"https://doi.org/10.1109/VLSID.2012.29","url":null,"abstract":"Reversible logic is emerging as a promising computing paradigm with applications in ultralow power nanocomputing and emerging nanotechnologies such as quantum computing, quantum dot cellular automata (QCA), optical computing, etc. Reversible circuits are similar to conventional logic circuits except that they are built from reversible gates. In reversible gates, there is a unique, one-to-one mapping between the inputs and outputs, not the case with conventional logic. One of the primary motivations for adopting reversible logic lies in the fact that it can provide a logic design methodology for designing ultra-low power circuits beyond KTln2 limit for those emerging nanotechnologies in which the energy dissipated due to information destruction will be a significant factor of the overall heat dissipation. Further, logic circuits for quantum computers must be built from reversible logic components. Several important metrics need to be considered in the design of reversible circuits the importance of which needs to be discussed. Quantum computers of many qubits are extremely difficult to realize thus the number of qubits in the quantum circuits needs to be minimized. This sets the major objective of optimizing the number of ancilla inputs and the number of the garbage outputs in the reversible logic based quantum circuits. The constant input in the reversible quantum circuit is called the ancilla input, while the garbage output refers to the output which exists in the circuit just to maintain one-to-one mapping but is not a primary or a useful output. The reversible circuit has other important parameters of quantum cost and delay which need to be optimized.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125295323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7