Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy

Abstract

In this paper, we propose a technique to improve the accuracy of the final design predicted by Geometric Programming based CMOS analog circuit sizing methodology. Here we use a multi-level AC performance modeling paradigm to develop the empirical models of circuit performance metrics. Performance models are then upgraded over iterations of design cycle. This iterative model up gradation in a sequence of geometric programming guides the final design to converge with better accuracy. The methodology is validated by designing a two-stage amplifier cascaded with a Class-A (source-follower) output buffer stage in UMC 0.18 μm technology.