Accurate Leakage Estimation for FinFET Standard Cells Using the Response Surface Methodology

Abstract

Among different multi-gate transistors, Fin FETs and Trigate FETs have set themselves apart as the most promising candidates for the upcoming 22nm technology node and beyond owing to their superior device performance, lower leakage power consumption and cost-effective fabrication process. Innovative circuit design and optimization techniques will be required to harness the power of multi-gate transistors, which in turn will depend on accurate leakage and timing characterization of these devices under spatial and environmental variations. Hence, in order to aid circuit designers, we present accurate analytical models using central composite rotatable design (CCRD) based on response surface methodology (RSM) to estimate the leakage current in Fin FET standard cells under the effect of variations in gate length (LG), fin thickness (TSI), gate-oxide thickness (TOX) and gate-work function (ΦG). To the best of our knowledge, this is the first attempt to develop analytical models for leakage estimation of Fin FET devices/logic gates based on TCAD simulations of adjusted 2D device cross-sections that have been shown to track TCAD simulations of 3D device behavior within a 1-3% error range. This drastically reduces the CPU time of our modeling technique (by several orders of magnitude) without much loss in accuracy. We present analytical leakage models for different logic styles, e.g., shorted-gate (SG) and independent-gate (IG) Fin FETs, at the 22nm technology node. The leakage estimates derived from the analytical models are in close agreement with quasi-Monte Carlo (QMC) simulation results obtained for different adjusted-2D (3D) devices/logic gates with a maximum root mean square error (RMSE) of 5.28% (7.03%).