C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas
{"title":"基于低功耗自重构多路复用器的自适应分辨率闪存adc解码器","authors":"C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas","doi":"10.1109/VLSID.2012.84","DOIUrl":null,"url":null,"abstract":"This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This 'self-reconfigurable' property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.","PeriodicalId":405021,"journal":{"name":"2012 25th International Conference on VLSI Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"22","resultStr":"{\"title\":\"Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs\",\"authors\":\"C. Vudadha, G. Makkena, M. Nayudu, P. Phaneendra, Syed Ershad Ahmed, S. Veeramachaneni, N. Muthukrishnan, M. Srinivas\",\"doi\":\"10.1109/VLSID.2012.84\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This 'self-reconfigurable' property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.\",\"PeriodicalId\":405021,\"journal\":{\"name\":\"2012 25th International Conference on VLSI Design\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-01-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"22\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 25th International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSID.2012.84\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 25th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2012.84","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs
This paper presents a new improved multiplexer based decoder for flash analog-to-digital converters. The proposed decoder is based on 2:1 multiplexers. It calculates the binary code for low operand length thermometer code at initial stages and groups the output of initial stages to generate the final result. The proposed decoder can be configured to operate on thermometer code with reduced length without any extra overhead. This 'self-reconfigurable' property is particularly useful in adaptive resolution analog-to-digital converters. Simulation results indicate that the proposed decoder results in reduced delay, power and power delay product when compared to existing digital decoders for flash analog-digital converters.