发布求助
文献互助 智能选刊 最新文献

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

筛选
英文 中文
Compact modeling of collector base junction space charge region transit time effect on noise in SiGe HBTs 集电极基极结空间电荷区传输时间对SiGe HBTs噪声影响的紧凑建模
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422988
Ziyan Xu, G. Niu, R. Malladi
{"title":"Compact modeling of collector base junction space charge region transit time effect on noise in SiGe HBTs","authors":"Ziyan Xu, G. Niu, R. Malladi","doi":"10.1109/SMIC.2010.5422988","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422988","url":null,"abstract":"This paper investigates the impact of collector-base space charge region (CB SCR) transport on RF noise in bipolar transistor using compact modeling. A model applicable to any compact models is derived and implemented using Verilog-A. Comparison with noise measurement on a SiGe HBT technology shows that overall the noise modeling results are much improved. The imaginary part of optimum generator admittance is slightly worse than without this effect.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"361 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115470867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Temperature calibration of a differential pair based direct digital synthesizer through subsampling spectral analysis 基于差分对的直接数字合成器的亚采样光谱校正
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422984
B. Laemmle, C. Wagner, H. Jaeger, R. Weigel
{"title":"Temperature calibration of a differential pair based direct digital synthesizer through subsampling spectral analysis","authors":"B. Laemmle, C. Wagner, H. Jaeger, R. Weigel","doi":"10.1109/SMIC.2010.5422984","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422984","url":null,"abstract":"The temperature behavior of a high speed direct digital synthesizer with a maximum clock frequency of 16.8GHz and a power consumption of 488mW at room temperature is investigated. The DDS has been manufactured in a 200-GHz ft SiGe bipolar technology and occupies a chip area of 1.15mm2. A subsampling approach is introduced to analyze the output spectrum of the DDS. A calibration is performed over temperature to improve the spectral performance of the DDS. The calibration is based on a two point measurement and the use of a look-up table. After calibration, the third harmonic is below 53 dBc and a narrow band SFDR is nearly constant at 38 dBc.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123864238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low value normally on RF-MEMS switched capacitor For high Q millimeter wave tuning 用于高Q值毫米波调谐的RF-MEMS开关电容
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422958
F. Barrière, A. Crunteanu, A. Pothier, M. Chatras, P. Blondy
{"title":"A low value normally on RF-MEMS switched capacitor For high Q millimeter wave tuning","authors":"F. Barrière, A. Crunteanu, A. Pothier, M. Chatras, P. Blondy","doi":"10.1109/SMIC.2010.5422958","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422958","url":null,"abstract":"RF-MEMS are allowing the practical fabrication of high Q tunable elements, such as tuners filters, or cavities. The MEMS capacitor can be switched between 14 fF and 4 fF, with a very low series resistance. Significant contrast could be obtained with extremely low value capacitances, and low series resistance.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116131418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Silicon integrated defected ground structures 硅集成缺陷地面结构
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422964
D. Schlieter, R. Henderson
{"title":"Silicon integrated defected ground structures","authors":"D. Schlieter, R. Henderson","doi":"10.1109/SMIC.2010.5422964","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422964","url":null,"abstract":"In this paper we study the impact of two common defected ground structures fabricated in finite ground coplanar waveguide on silicon and alumina substrates useful for monolithic and hybrid designs. The single defects resonate at 30GHz and have bandwidth differences due to the nature and size of the defect. On-wafer measurements up to 40GHz are included for the silicon designs and show good agreement with simulation.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"370 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133082483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High gain, high linearity, L-band SiGe low noise amplifier with fully-integrated matching network 高增益，高线性，l波段SiGe低噪声放大器，具有完全集成的匹配网络
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422953
J. Poh, P. Cheng, T. Thrivikraman, J. Cressler
{"title":"High gain, high linearity, L-band SiGe low noise amplifier with fully-integrated matching network","authors":"J. Poh, P. Cheng, T. Thrivikraman, J. Cressler","doi":"10.1109/SMIC.2010.5422953","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422953","url":null,"abstract":"This paper presents an L-band silicon-germanium (SiGe) low-noise amplifier (LNA) for use in Global Positioning System (GPS) receivers. Implemented in a 200 GHz SiGe BiCMOS technology, the LNA occupies 1 × 1 mm2 (including the bondpads). The SiGe LNA exhibits a gain greater than 23 dB from 1.1 to 2.0 GHz, and a noise figure of 2.7 to 3.3 dB from 1.2 to 2.4 GHz. At 1.575 GHz, the 1-dB compression point (P1dB) is 1.73 dBm, with an input third-order intercept point (IIP3) of −3.98 dBm.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131026455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 2.4 GHz 0.18-µm CMOS Class E single-ended power amplifier without spiral inductors 2.4 GHz 0.18µm CMOS E类单端功率放大器，无螺旋电感
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422842
S. Murad, R. Pokharel, H. Kanaya, K. Yoshida
{"title":"A 2.4 GHz 0.18-µm CMOS Class E single-ended power amplifier without spiral inductors","authors":"S. Murad, R. Pokharel, H. Kanaya, K. Yoshida","doi":"10.1109/SMIC.2010.5422842","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422842","url":null,"abstract":"This paper describes the design of a 2.4-GHz CMOS Class E single-ended power amplifier (PA) for wireless applications in TSMC 0.18-µm CMOS technology. The Class E PA proposed in this paper realizes all inductors with bondwires for the higher quality factor to increase PA performance and to reduce chip size. The single-ended topology is employed because most existing components designed to be driven by PAs are single-ended. The cascode topology with a self-biasing technique is used to prevent device stress and to decrease the requirement for additional bond pads. The measurement results indicate that the PA delivers 19.2 dBm output power and 27.8% power added efficiency with 3.3-V power supply into a 50 Ω load. The chip area is 0.37 mm2.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131994816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An integrated fractional-N frequency synthesizer for software-defined radio applications 用于软件定义无线电应用的集成分数n频率合成器
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422947
S. Osmany, F. Herzel, J. Scheytt
{"title":"An integrated fractional-N frequency synthesizer for software-defined radio applications","authors":"S. Osmany, F. Herzel, J. Scheytt","doi":"10.1109/SMIC.2010.5422947","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422947","url":null,"abstract":"We present an integrated fractional-N frequency synthesizer providing in-phase / quadrature phase signal over the frequency bands 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and in-phase signal over 20–28 GHz for software-defined radio applications. An integrated voltage controlled oscillator (VCO) with 34 % tuning range and a set of high speed dividers are used to accomplish all the frequencies. By employing a multi-bit, single-loop sigma delta modulator and an 8-bit reference divider, the synthesizer can achieve a frequency step size of less than 10 Hz. The measured PLL phase noise is −132 dBc/Hz and −121 dBc/Hz at 1 MHz offset for 884 MHz and 3.5 GHz, respectively. Fabricated in a 0.25 µm SiGe-BiCMOS process, the VCO including buffer draws 45 mA from a 5 V supply and the rest draws 150 mA from a 3 V supply.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114723522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
TFMS Microstrip line modelling and characterization up to 110 GHz on 45 nm node silicon technology: application for CAD 45纳米节点硅技术上高达110 GHz的微带线建模和表征:CAD应用
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422850
T. Quemerais, L. Moquillon, J. Fournier, P. Benech, N. Corrao
{"title":"TFMS Microstrip line modelling and characterization up to 110 GHz on 45 nm node silicon technology: application for CAD","authors":"T. Quemerais, L. Moquillon, J. Fournier, P. Benech, N. Corrao","doi":"10.1109/SMIC.2010.5422850","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422850","url":null,"abstract":"An improved analytical model for integrated microstrip line experienced on 45 nm silicon technology is proposed. This model is derived from previous classical ones used for PCB circuits. Improvements have been performed to take into account the sizing effects for integrated lines. The study is performed up to 110 GHz for different line widths and results accuracy allow implementing the model in CAD software like Eldo, Spectre and the Agilent tools (RFDE, ADS, and GoldenGate) for mm-wave designs.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129649882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Further generalized four-port de-embedding method by dropping ideality assumptions on the THROUGH structure 通过放弃对直通结构的理想性假设，进一步推广了四端口去嵌入方法
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422976
K. Xia, G. Niu, Xiaoyun Wei
{"title":"Further generalized four-port de-embedding method by dropping ideality assumptions on the THROUGH structure","authors":"K. Xia, G. Niu, Xiaoyun Wei","doi":"10.1109/SMIC.2010.5422976","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422976","url":null,"abstract":"Four-port on-wafer de-embedding is necessary for on-wafer measurement at frequencies above 50 GHz. We found notable discrepancy between the Y-parameters de-embedded using different options provided by a recently published general four-port de-embedding algorithm to solve the four-port Y-parameter matrices. The problem is caused by the ideality assumptions on the internal THROUGH test structure. In this paper, we develop a further generalized algorithm that drops any ideality assumption except passivity on the THROUGH structure. The new method works for transistor S-parameters with or without Impedance Standard Substrate calibration.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123904635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A deep silicon via (DSV) ground for sige power amplifiers 用于大功率放大器的深硅通孔(DSV)地
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422966
V. Blaschke, T. Thibeault, L. Lanzerotti, C. Cureton, R. Zwingman, A. Karroy, E. Preisler, D. Howard, M. Racanelli
{"title":"A deep silicon via (DSV) ground for sige power amplifiers","authors":"V. Blaschke, T. Thibeault, L. Lanzerotti, C. Cureton, R. Zwingman, A. Karroy, E. Preisler, D. Howard, M. Racanelli","doi":"10.1109/SMIC.2010.5422966","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422966","url":null,"abstract":"A low parasitic inductance ground for SiGe power amplifiers has been implemented using a deep silicon via (DSV). The advantages and opportunities that this approach opens for the power amplifier (PA) design process are demonstrated. DSV resistance, inductance, and data from IV sweep, RF characterization and loadpull measurements are analyzed.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122920478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信