{"title":"Four-wires shunt active filters: optimized design methodology","authors":"A. Cavini, F. Ronchi, A. Tilli","doi":"10.1109/IECON.2003.1280601","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280601","url":null,"abstract":"This paper deals with the design of a four-wire shunt active filter (SAF) based on a AC/DC converter. Different methodologies in choosing suitable values of the components, both inductor and capacitor, are presented for different objectives. The first two present a procedure to design the inductor limiting the current ripple of the filter. The others deal with the capacitor design: the first solution is based on the knowledge of the load spectrum, while the second one regards the worst load case for a given maximum current of the inverter switches. Both the algorithms are based on a model inversion and are control-oriented.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131345429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved genetic algorithm for economic load dispatch with valve-point loadings","authors":"S. Ling, H.K. Lam, F. Leung, Y.S. Lee","doi":"10.1109/IECON.2003.1280021","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280021","url":null,"abstract":"Economic load dispatch is one of the optimization problems in power systems. This paper presents an improved genetic algorithm for economic load dispatch with valve-point loadings. New crossover and mutation operations are introduced. The solutions of the economic load dispatch with valve-point loadings under three cases are solved by the improved genetic algorithm. Test results are given and compared with those from different published genetic algorithms. It is shown that the proposed improved genetic algorithm performs better than the published genetic algorithms.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132051808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of conventional/improved delta modulators as switched dynamical systems","authors":"H. Shimazu, T. Saito, H. Torikai","doi":"10.1109/IECON.2003.1280338","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280338","url":null,"abstract":"This paper studies dynamics of the delta modulators (DM) and its improvement. The dynamics can be simplified into a 1-D return map, a simple differential equation. Using the return map, we clarify the mechanism for the non-synchronous operation and pulse-dropping phenomenon theoretically. We present a stabilization method of the synchronous phenomena using periodic compulsory switchings. Using a simple test circuit, typical operations are verified in the laboratory.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130169985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Digital controller design for buck and boost converters using root locus techniques","authors":"Liping Guo, John Y. Hung, R. Nelms","doi":"10.1109/IECON.2003.1280344","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280344","url":null,"abstract":"Root locus techniques to design digital controllers for buck and boost converters are discussed in this paper. The small signal models of both converters are first transformed into discrete-time models using the matched pole-zero mapping method. Digital controllers are designed based on the discrete-time model using the root locus method. By selecting the poles, zeros and gain of the digital controllers, the closed-loop poles are placed at desired locations in the z-plane. The digital controllers are then implemented on a TI DSP. The root locus design method is compared with the frequency response design method. Experimental results from the buck converter indicate that the results obtained using the root locus method are comparable to the results obtained using the frequency response method, while results from the boost converter indicate the nonlinear nature of the boost converter small signal model may degrade the performance of the design using the root locus method.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134600985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new high accuracy software based resolver-to-digital converter","authors":"A. D. Di Tommaso, R. Miceli","doi":"10.1109/IECON.2003.1280627","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280627","url":null,"abstract":"Tracking resolver-to-digital conversion (R/D converter or simply RDC) has emerged as one of the most robust method for obtaining high resolution position and angular speed information from resolvers. In this paper low cost software based RDC is presented. The main features are: high accuracy, simple set up, high reliability and stability and good performances. Some experimental results, showing the capabilities of the proposed system, are presented and discussed. An output signal comparison between the proposed RDC and a commercial encoder is also presented.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131784382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Warpage detection during baking of semiconductor substrate in microlithography","authors":"W. Ho, A. Tay, K. Lim, Ying Zhou, Kai Yang","doi":"10.1109/IECON.2003.1280598","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280598","url":null,"abstract":"Wafer warpage is common in microelectronics processing. Warped wafers can affect driven performance, reliability and linewidth control in various processing steps. We proposed in this paper an in-situ fault detection technique for wafer warpage in microlithography. Early detection can minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility of the approach. The proposed approach is applicable to other semiconductor substrates.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129387663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Control of active filters using source current detection","authors":"T. Takeshita, N. Matsui","doi":"10.1109/IECON.2003.1280282","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280282","url":null,"abstract":"This paper presents a control scheme of the shunt active filters using the source current detection to suppress the source current harmonics. The proposed control scheme can minimize the source current harmonics under the given active filter capacity, which can be realized by adjusting the magnitude and phase of the compensation current using the complex compensation gains in the frequency domain. The effectiveness of the proposed control scheme has been verified by experiments. As a result, the good effect on the compensation for the source harmonic currents in the proposed control scheme is obtained compared with that in the conventional one.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117314932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An effective approach to predict performances of high speed BLDC motors in hard disk drives","authors":"Q. Jiang, C. Bi, A. Al Mamum","doi":"10.1109/IECON.2003.1280570","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280570","url":null,"abstract":"As the speed of the BLDC motors in hard disk drives has been increased from 3,600 rpm to 15,000 rpm, the phase commutation of the motor and the MOSFET switches of inverter influence the spindle motor performances obviously, for examples, the torque ripple and efficiency of the motor. In this paper, an effective approach of BLDC spindle motor system is presented to predict the performance of BLDC motors accurately. Both the characteristics of the spindle motor and MOSFET switches of the inverter can be taken into account in the simulation. The experimental results confirmed the effectiveness of the proposed method.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130974719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Astarloa, U. Bidarte, A. Zuloaga, I. M. D. Alegria
{"title":"Reconfigurable microstepping control of stepper motors using FPGA embedded RAM","authors":"A. Astarloa, U. Bidarte, A. Zuloaga, I. M. D. Alegria","doi":"10.1109/IECON.2003.1280588","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280588","url":null,"abstract":"The control of stepper motors using microsteps in open-loop systems is a well known mechanical and electrical improvement. The most common stepper motor controllers have all the elements to perform a microstepping control requiring only the digital control for the current level and direction in each winding. In this design we propose a cost-effective solution to integrate this control into high speed FPGA based designs. The core uses an FPGA block RAM to save conventional logic resources. Also, if the system needs to change the microstepping control granularity while the system is running, a partial dynamic reconfiguration can be performed only by changing the content of the block RAM attached to the core.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132872897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hysteresis current regulation for single-phase multilevel inverters using asynchronous state machines","authors":"G. Bode, D. G. Holmes","doi":"10.1109/IECON.2003.1280224","DOIUrl":"https://doi.org/10.1109/IECON.2003.1280224","url":null,"abstract":"This paper describes the use of asynchronous state machines for the hysteresis current regulation of multi-level inverters. The state machines exploit the redundant states in order to balance the switching losses between the semiconductor devices, and to balance the voltages across the capacitors of topologies with series connected capacitors. The current regulators achieve a robust transient and steady state operation that fully utilises both the multiple DC levels available and the redundant states. Theory, simulation and experimental results are presented.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133566449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}