A. Astarloa, U. Bidarte, A. Zuloaga, I. M. D. Alegria
{"title":"Reconfigurable microstepping control of stepper motors using FPGA embedded RAM","authors":"A. Astarloa, U. Bidarte, A. Zuloaga, I. M. D. Alegria","doi":"10.1109/IECON.2003.1280588","DOIUrl":null,"url":null,"abstract":"The control of stepper motors using microsteps in open-loop systems is a well known mechanical and electrical improvement. The most common stepper motor controllers have all the elements to perform a microstepping control requiring only the digital control for the current level and direction in each winding. In this design we propose a cost-effective solution to integrate this control into high speed FPGA based designs. The core uses an FPGA block RAM to save conventional logic resources. Also, if the system needs to change the microstepping control granularity while the system is running, a partial dynamic reconfiguration can be performed only by changing the content of the block RAM attached to the core.","PeriodicalId":403239,"journal":{"name":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-11-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IECON'03. 29th Annual Conference of the IEEE Industrial Electronics Society (IEEE Cat. No.03CH37468)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECON.2003.1280588","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
The control of stepper motors using microsteps in open-loop systems is a well known mechanical and electrical improvement. The most common stepper motor controllers have all the elements to perform a microstepping control requiring only the digital control for the current level and direction in each winding. In this design we propose a cost-effective solution to integrate this control into high speed FPGA based designs. The core uses an FPGA block RAM to save conventional logic resources. Also, if the system needs to change the microstepping control granularity while the system is running, a partial dynamic reconfiguration can be performed only by changing the content of the block RAM attached to the core.