2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)最新文献

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Irregular pupil localization using connected component analysis 利用连通分量分析进行不规则瞳孔定位
J. J. Fernandez, A. Mathew
{"title":"Irregular pupil localization using connected component analysis","authors":"J. J. Fernandez, A. Mathew","doi":"10.1109/IMAC4S.2013.6526399","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526399","url":null,"abstract":"Irregular pupil boundary localization is proposed in this paper by designing a new approach that extracts the irregular pupil boundary points from the edge map using 4-neighborhood connected component analysis. Initially, Canny's edge detection is adopted to extract the edge map in the eye image. Then the proposed boundary extraction technique is employed to extract the pupil boundary points perfectly and it is independent of the specific eye image characteristics such as pupil deformation, poor contrast, poor brightness, etc., The proposed approach is adaptable to all monochrome databases and exhibits encouraging results when compared with the existing techniques.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131966721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Preprocessing and training effects in voltage stability assessment using neural networks 神经网络在电压稳定性评估中的预处理和训练效果
A. Francis, T. Joseph, L. Salim
{"title":"Preprocessing and training effects in voltage stability assessment using neural networks","authors":"A. Francis, T. Joseph, L. Salim","doi":"10.1109/IMAC4S.2013.6526404","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526404","url":null,"abstract":"We present the effects of preprocessing and training parameters in stability index computation using neural network. Two method of index computation was done. In first method active and reactive power are given as net inputs and bus voltage is set as target. From the predicted bus voltage, stability index is computed. In the second method P, Q, V and power factor is given as input and L-index is given as the net output. We show that preprocessing, the raw data with more number of input parameters makes more effective index computation. We also propose the optimum training parameters of the network, based on experimental observation.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117154628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel high speed vedic mathematics multiplier using compressors 采用压缩机的新型高速韦达数学乘法器
Sushma R. Huddar, S. R. Rupanagudi, Surabhi Mohan
{"title":"Novel high speed vedic mathematics multiplier using compressors","authors":"Sushma R. Huddar, S. R. Rupanagudi, Surabhi Mohan","doi":"10.1109/IMAC4S.2013.6526456","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526456","url":null,"abstract":"With the advent of new technology in the fields of VLSI and communication, there is also an ever growing demand for high speed processing and low area design. It is also a well known fact that the multiplier unit forms an integral part of processor design. Due to this regard, high speed multiplier architectures become the need of the day. In this paper, we introduce a novel architecture to perform high speed multiplication using ancient Vedic maths techniques. A new high speed approach utilizing 4:2 compressors and novel 7:2 compressors for addition has also been incorporated in the same and has been explored. Upon comparison, the compressor based multiplier introduced in this paper, is almost two times faster than the popular methods of multiplication. With regards to area, a 1% reduction is seen. The design and experiments were carried out on a Xilinx Spartan 3e series of FPGA and the timing and area of the design, on the same have been calculated.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124707160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 94
Analysis of physiological signals in response to stress using ECG and respiratory signals of automobile drivers 利用心电和呼吸信号分析汽车驾驶员应激反应的生理信号
Karthik Soman, V. Alex, C. Srinivas
{"title":"Analysis of physiological signals in response to stress using ECG and respiratory signals of automobile drivers","authors":"Karthik Soman, V. Alex, C. Srinivas","doi":"10.1109/IMAC4S.2013.6526476","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526476","url":null,"abstract":"This paper gives an analysis of variation of the physiological signals of a person with respect to the stress developed within him/her. The analysis was done using ECG and respiratory signals acquired from the automobile drivers who were made to drive on different road conditions to get different stress levels. As a part of analysis, we extracted two feature signals from the above said physiological signals. QRS power spectrum and the breathing rate were the two feature signals that were extracted from the mentioned physiological signals. Heart rate was used as the marker signal for analyzing the variations in the extracted physiological feature signals. The variations in the feature signals with respect to the stress were expressed in terms of correlation coefficients and were tabulated. The analysis clearly showed the changes in the feature signals with respect to the stress of the driver. It showed a direct proportionate relation in the QRS power and the breathing rate with respect to the stress of the driver. The analysis also showed that QRS power signal is a better feature signal for analyzing the stress since it showed more correlation with the heart rate marker signal. The analysis points out the fact that the physiological signals can be used as a metric for monitoring the stress of a person.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115216618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A novel algorithmic approach for logic synthesis engine design 一种新的逻辑合成引擎设计算法
H. Arora, A. Banerjee, R. R. Jidge
{"title":"A novel algorithmic approach for logic synthesis engine design","authors":"H. Arora, A. Banerjee, R. R. Jidge","doi":"10.1109/IMAC4S.2013.6526513","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526513","url":null,"abstract":"Logic Synthesis is a novel architectural method used in VLSI design cycle by which technology independent, architectural and algorithmic high level description (like: RTL: Register Transfer Level) of a complex electronic circuit is converted into optimized gate (transistor) level netlist. In Boolean algebraic factorization, a logic expression is considered as polynomials. The conventional methods, like: Truth table, K-Map, SOP and POS forms yield satisfactory results for the Boolean functions comprises of AND/OR expressions. But these methods are not able to derive optimal Boolean factorization for Multiplexer and AND/OR/XOR intensive functions. In the proposed work, we plan to investigate and analyze wide detailed insight into a state of the art minimization algorithm employing data structure to form the basis for synthesis engine. We plan to go step by step of a Binary Decision Diagram (BDD) formation and reduction and will analyze in detail for optimal and enhanced performance. As the time and space complexities of the circuit greatly depend on the number of nodes of the BDD, a proper ordering of the input variables is essential to derive the optimal ROBDD (Reduce Ordered BDD). Our work plans to propose a heuristic approach to derive proper ordering of the input variables for BDD tree with minimum computation to reduce the space complexity of the circuit.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117018071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modified FPGA based design and implementation of reconfigurable FFT architecture 基于改进FPGA的可重构FFT体系结构设计与实现
R. Bhakthavatchalu, A. Kripalal, S. Nair, P. Venugopal, M. Viswanath
{"title":"Modified FPGA based design and implementation of reconfigurable FFT architecture","authors":"R. Bhakthavatchalu, A. Kripalal, S. Nair, P. Venugopal, M. Viswanath","doi":"10.1109/IMAC4S.2013.6526519","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526519","url":null,"abstract":"Fast Fourier Transforms, popularly known as FFTs, have become an integral part of any digital communication system and a wide variety of approaches have been tried in order to optimize the algorithm for a variety of parameters, primarily Area, Memory and Speed. The aim is to build a Reconfigurable Fast Fourier Transform Block which is suitable for any signal processing application, especially for communication blocks such as OFDM receivers. The objective is to design an FFT block that is capable of computing any N-point FFT and employs R2SDF (Radix 2 Single Delay Feedback) architecture with a single ROM. The design has been developed using the hardware description language VHDL on Xilinx xc5vlx110t. The result shows significant reduction in area for this architecture.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129899772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Leaky least mean square (LLMS) algorithm for channel estimation in BPSK-QPSK-PSK MIMO-OFDM system BPSK-QPSK-PSK MIMO-OFDM系统信道估计的泄漏最小均方(LLMS)算法
D. Bhoyar, C. Dethe, M. Mushrif, A. Narkhede
{"title":"Leaky least mean square (LLMS) algorithm for channel estimation in BPSK-QPSK-PSK MIMO-OFDM system","authors":"D. Bhoyar, C. Dethe, M. Mushrif, A. Narkhede","doi":"10.1109/IMAC4S.2013.6526485","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526485","url":null,"abstract":"In broadband wireless channel multiple-input multiple-output (MIMO) communication system combined with the orthogonal frequency division multiplexing (OFDM) modulation technique can achieve reliable high data rate transmission and to mitigate intersymbol interference. High data rate system suffer from inter symbol interference (ISI). To estimate the desire channel at the receiver channel Estimation techniques are used and also enhance system capacity of system. The MIMO-OFDM system uses two independent space-time codes for two sets of two transmit antennas. The objective of this paper is to improve channel estimation accuracy in MIMO-OFDM system because channel state information is required for signal detection at receiver and its accuracy affects the overall performance of system and it is essential for reliable communication. This paper presents channel estimation scheme based on Leaky Least Mean Square (LLMS) algorithm proposed for BPSK-QPSK-PSK MIMO OFDM System. So by designing this we are going to analyze the terms of the Minimum Mean Squares Error (MMSE), and Bit Error Rate (BER) and improve Signal to Noise Ratio.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124237317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A low-noise amplifier design for 3.1–10.6 GHz impulse radio ultra wideband receivers 3.1-10.6 GHz脉冲无线电超宽带接收机的低噪声放大器设计
A. Adsul, S. Bodhe
{"title":"A low-noise amplifier design for 3.1–10.6 GHz impulse radio ultra wideband receivers","authors":"A. Adsul, S. Bodhe","doi":"10.1109/IMAC4S.2013.6526457","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526457","url":null,"abstract":"In this paper the LNA is designed to amplify the radio-signals received in the UWB band (3.1-10.6 GHz) with a good signal-to-noise ratio property, high and flat power gain, good input impedance matching and good phase linearity. The 0.4 μm CMOS technology is used for implementation. A detailed designed is carried for the LNA and is simulated on ADS. The simulation results demonstrate that the gain is flat over the band of interest and is of the order of 12 dB. The noise figure of the designed LNA is good and is in the range of 3.35 to 2.8 dB. The most important achievement is the linearity which is decided by group delay and this implementation achieves group delay variations in the range of ± 12.175 ps.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116509476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Studies on electrical conductivity of PVC-Graphite thick film resistors pvc -石墨厚膜电阻器的电导率研究
B. Poornaiah, B. Rambabu, K. Subrahmanyam, Y. Srinivasarao
{"title":"Studies on electrical conductivity of PVC-Graphite thick film resistors","authors":"B. Poornaiah, B. Rambabu, K. Subrahmanyam, Y. Srinivasarao","doi":"10.1109/IMAC4S.2013.6526459","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526459","url":null,"abstract":"The variation of electrical conductivity of PVC-Graphite thick film resistors, with parameters such as volume fraction and grain size has been studied. The conductivity of PVC-graphite thick film resistors are calculated using Scarisbrick's model of the conductivity of mixtures.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128014330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the design of Trojan tolerant finite field multipliers 耐特洛伊有限域乘法器的设计
C. T. Veedon, M. Poolakkaparambil, A. Jabir, J. Mathew
{"title":"On the design of Trojan tolerant finite field multipliers","authors":"C. T. Veedon, M. Poolakkaparambil, A. Jabir, J. Mathew","doi":"10.1109/IMAC4S.2013.6526453","DOIUrl":"https://doi.org/10.1109/IMAC4S.2013.6526453","url":null,"abstract":"In this paper we analyze the process variation in different multiplier circuits and describe techniques to design error correcting circuits. Integrated circuits have reached such a level of integration that the length transistors is limited to 10s of nanometres. The increasing difficulty to fabricate millions of transistors of the same parameters specified in the integrated circuit design have lead to variation in the performance of the integrated circuit, for instance the thickness of the gate oxide, the length and width of the of the transistor, the doping concentration in the N well substrate, gate threshold voltage and so on. This process variation can be misused for Trojan attacks. Trojan attacks are based on injecting some fault in to the cryptosystem and observing any leak of information by analyzing the erroneous results due to the additional Trojan circuitry. In order to avoid such fault-based attacks, the cryptosystem can be used to detect errors and correct computations, thereby not producing any erroneous results as output. In this paper we further discuss about the error correcting finite field multiplier, as on-line error correction is done it results in more robust hardware modules. The Trojan circuitry can be added even after the error correction stage and hence we have designed a new technique such that error detection and correction is done irrespective of the position of the Trojan in the multiplier.","PeriodicalId":403064,"journal":{"name":"2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125981231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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