A novel algorithmic approach for logic synthesis engine design

Abstract

Logic Synthesis is a novel architectural method used in VLSI design cycle by which technology independent, architectural and algorithmic high level description (like: RTL: Register Transfer Level) of a complex electronic circuit is converted into optimized gate (transistor) level netlist. In Boolean algebraic factorization, a logic expression is considered as polynomials. The conventional methods, like: Truth table, K-Map, SOP and POS forms yield satisfactory results for the Boolean functions comprises of AND/OR expressions. But these methods are not able to derive optimal Boolean factorization for Multiplexer and AND/OR/XOR intensive functions. In the proposed work, we plan to investigate and analyze wide detailed insight into a state of the art minimization algorithm employing data structure to form the basis for synthesis engine. We plan to go step by step of a Binary Decision Diagram (BDD) formation and reduction and will analyze in detail for optimal and enhanced performance. As the time and space complexities of the circuit greatly depend on the number of nodes of the BDD, a proper ordering of the input variables is essential to derive the optimal ROBDD (Reduce Ordered BDD). Our work plans to propose a heuristic approach to derive proper ordering of the input variables for BDD tree with minimum computation to reduce the space complexity of the circuit.