On the design of Trojan tolerant finite field multipliers

Abstract

In this paper we analyze the process variation in different multiplier circuits and describe techniques to design error correcting circuits. Integrated circuits have reached such a level of integration that the length transistors is limited to 10s of nanometres. The increasing difficulty to fabricate millions of transistors of the same parameters specified in the integrated circuit design have lead to variation in the performance of the integrated circuit, for instance the thickness of the gate oxide, the length and width of the of the transistor, the doping concentration in the N well substrate, gate threshold voltage and so on. This process variation can be misused for Trojan attacks. Trojan attacks are based on injecting some fault in to the cryptosystem and observing any leak of information by analyzing the erroneous results due to the additional Trojan circuitry. In order to avoid such fault-based attacks, the cryptosystem can be used to detect errors and correct computations, thereby not producing any erroneous results as output. In this paper we further discuss about the error correcting finite field multiplier, as on-line error correction is done it results in more robust hardware modules. The Trojan circuitry can be added even after the error correction stage and hence we have designed a new technique such that error detection and correction is done irrespective of the position of the Trojan in the multiplier.