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Proceedings. 42nd Design Automation Conference, 2005.最新文献

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Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy constraints 具有能量约束的实时系统中奖励最大化的准静态电压分配和可选周期
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065813
L. Cortés, P. Eles, Zebo Peng
{"title":"Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy constraints","authors":"L. Cortés, P. Eles, Zebo Peng","doi":"10.1145/1065579.1065813","DOIUrl":"https://doi.org/10.1145/1065579.1065813","url":null,"abstract":"There exist real-time systems for which it is possible to trade off precision for timeliness. In these cases, a function assigns reward to the application depending on the amount of computation allotted to it. At the same time, many such applications run on battery-powered devices with stringent energy constraints. This paper addresses the problem of maximizing rewards subject to time and energy constraints. We propose a quasi-static approach where the problem is solved in two steps: first, at design-time, a number of solutions are computed and stored (off-line phase); second, one of the precomputed solutions is selected at run-time based on actual values of time and energy (on-line phase). Thus our approach is able to exploit, with low on-line overhead, the dynamic slack caused by tasks executing less number of cycles than in the worst case. We conduct numerous experiments in order to show the advantages of our approach.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128539296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements 具有复杂QoS要求的基于FPGA的SDRAM控制器的流量整形
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065729
S. Heithecker, R. Ernst
{"title":"Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements","authors":"S. Heithecker, R. Ernst","doi":"10.1145/1065579.1065729","DOIUrl":"https://doi.org/10.1145/1065579.1065729","url":null,"abstract":"Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multi-stream access with different QoS requirements is involved. In (Heithecker et al., 2003), a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard real-time constraints for periodic video signals and hard real-time bursty accesses for video coprocessors was described. To handle these contradictory QoS requirements at high system performance, a combination of a 2-stage scheduling algorithm and static priorities were used. This paper describes an additional flow control which enhances the overall performance. Experiments with an FPGA based high-end video platform demonstrate the superiority of this architecture.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"10 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129063909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC Paper 24.3) 基于64800位LDPC和BCH码的135Mbps DVB-S2兼容编解码器(ISSCC Paper 24.3)
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065721
P. Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta
{"title":"A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC Paper 24.3)","authors":"P. Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta","doi":"10.1145/1065579.1065721","DOIUrl":"https://doi.org/10.1145/1065579.1065721","url":null,"abstract":"A DVB-S2 compliant codec is implemented in both 130nm-8M and 90nm-7M low-leakage CMOS technologies. The system includes encoders and decoders for both low-density parity check (LDPC) codes and serially concatenated BCH codes. All requirements of the DVB-S2 standard are supported including code rates between 1/4 and 9/10, block sizes of either 16,200 bits or 64,800 bits, and four digital modulation options. The 130nm core design occupies 49.6mm2 and operates at 200MHz, while the 90nm core design occupies 15.8mm2 and operates at 300MHz.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114498349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Effective bounding techniques for solving unate and binate covering problems 解决一元和二元覆盖问题的有效边界技术
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065682
Xiao Yu Li, Matthias F. Stallmann, F. Brglez
{"title":"Effective bounding techniques for solving unate and binate covering problems","authors":"Xiao Yu Li, Matthias F. Stallmann, F. Brglez","doi":"10.1145/1065579.1065682","DOIUrl":"https://doi.org/10.1145/1065579.1065682","url":null,"abstract":"Covering problems arise in many areas of electronic design automation such as logic minimization and technology mapping. An exact solution can critically impact both size and performance of the devices being designed. This paper introduces eclipse, a branch-and-bound solver that can solve many covering problems orders of magnitude faster than existing solvers. When used in place of the default covering engine of a well-known logic minimizer, eclipse makes it possible to find, in less than six minutes, true minima for three benchmark problems that have eluded exact solutions for more than a decade.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114796903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition 不完全指定多输出逻辑函数的BDD表示及其在功能分解中的应用
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065680
Tsutomu Sasao, M. Matsuura
{"title":"BDD representation for incompletely specified multiple-output logic functions and its applications to functional decomposition","authors":"Tsutomu Sasao, M. Matsuura","doi":"10.1145/1065579.1065680","DOIUrl":"https://doi.org/10.1145/1065579.1065680","url":null,"abstract":"A multiple-output function can be represented by a binary decision diagram for characteristic function (BDD/spl I.bar/for/spl I.bar/CF). This paper presents a new method to represent multiple-output incompletely specified functions using BDD/spl I.bar/for/spl I.bar/CF. An algorithm to reduce the widths of BDD/spl I.bar/for/spl I.bar/CFs is presented. This method is useful for decomposition of incompletely specified multiple-output functions. Experimental results for radix converters, adders and a multiplier show that this method is useful for the synthesis of LUT cascades. This data structure is also useful to three-valued logic simulation.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126635585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
How accurately can we model timing in a placement engine? 我们在放置引擎中如何精确地建模时间?
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065792
Amit Chowdhary, K. Rajagopal, S. Venkatesan, Tung Cao, V. Tiourin, Yegna Parasuram, Bill Halpin
{"title":"How accurately can we model timing in a placement engine?","authors":"Amit Chowdhary, K. Rajagopal, S. Venkatesan, Tung Cao, V. Tiourin, Yegna Parasuram, Bill Halpin","doi":"10.1145/1065579.1065792","DOIUrl":"https://doi.org/10.1145/1065579.1065792","url":null,"abstract":"This paper presents a novel placement algorithm for timing optimization based on a new and powerful concept, which we term differential timing analysis. Recognizing that accurate optimization requires timing information from a signoff static timing analyzer, we propose an incremental placement algorithm that uses timing information from a signoff static timing engine. We propose a set of differential timing analysis equations that accurately capture the effect of placement perturbations on changes in timing from the signoff timer. We have formulated an incremental placement optimization problem based on differential timing analysis as a single linear programming (LP) problem which is solved to generate the new timing-optimized placement. Our experiments show that the worst negative slack (WNS) improves by an average of 30% and the total negative slack (TNS) improves by 33% on average for a set of circuits from a 3.0 GHz microprocessor that were already synthesized and placed by a leading industrial physical synthesis tool. We also show that multiple iterations of our engine give further TNS improvements - an average improvement of 51%, which implies that our placer will significantly speed up timing convergence.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126894991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 49
DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures DiMES:基于多极展开的大规模耦合三维微电子结构寄生提取的多级快速直接求解器
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065622
D. Gope, I. Chowdhury, V. Jandhyala
{"title":"DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures","authors":"D. Gope, I. Chowdhury, V. Jandhyala","doi":"10.1145/1065579.1065622","DOIUrl":"https://doi.org/10.1145/1065579.1065622","url":null,"abstract":"Boundary element methods are being successfully used for modeling parasitic effects in cutting-edge circuit design. The dense system matrix generated therein presents a time and memory bottleneck. Fast iterative solver techniques, developed to address the problem, suffer from convergence issues which become pronounced for large number of right hand sides as is the case for massively coupled systems. In this paper an iteration free solution scheme is presented. The dense matrix is rendered sparse by applying multilevel multipole expansions, and the resultant sparse matrix is solved by a traditional sparse matrix solver. The accuracy and time and memory requirements for the solver are compared against the regular methods. The advantage of the presented method over the corresponding iterative scheme is also demonstrated.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"173 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124249589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Timing-driven placement by grid-warping 通过网格翘曲的时间驱动放置
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065732
Zhong Xiu, Rob A. Rutenbar
{"title":"Timing-driven placement by grid-warping","authors":"Zhong Xiu, Rob A. Rutenbar","doi":"10.1145/1065579.1065732","DOIUrl":"https://doi.org/10.1145/1065579.1065732","url":null,"abstract":"Grid-warping is a recent placement strategy based on a novel physical analogy: rather than move the gates to optimize their location, it elastically deforms a model of the 2-D chip surface on which the gates have been coarsely placed via a standard quadratic solve. In this paper, we introduce a timing-driven grid-warping formulation that incorporates slack-sensitivity-based net weighting. Given inevitable concerns about wirelength and runtime degradation in any timing-driven scheme, we also incorporate a more efficient net model and an integrated local improvement (\"rewarping\") step. An implementation of these ideas, Warp2, can improve worst-case negative slack by 37% on average, with very modest increases in wirelength and runtime.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123419575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Modular domain-specific implementation and exploration framework for embedded software platforms 面向嵌入式软件平台的模块化特定领域实现与探索框架
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065646
C. Sauer, M. Gries, Sören Sonntag
{"title":"Modular domain-specific implementation and exploration framework for embedded software platforms","authors":"C. Sauer, M. Gries, Sören Sonntag","doi":"10.1145/1065579.1065646","DOIUrl":"https://doi.org/10.1145/1065579.1065646","url":null,"abstract":"This paper focuses on designing network processing software for embedded processors. Our design flow CRACC represents an efficient path to implementation based on a modular application description, while avoiding much of the overhead of existing component-based techniques. We illustrate results for a real-world application implementing a full IP-based DSL access multiplexer (IP-DSLAM) system. We quantify overhead and optimization potential incurred by our modular implementation. We also point out how CRACC can be deployed for HW-SW partitioning and design space exploration.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123220398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
System-level energy-efficient dynamic task scheduling 系统级节能动态任务调度
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065744
Jianli Zhuo, C. Chakrabarti
{"title":"System-level energy-efficient dynamic task scheduling","authors":"Jianli Zhuo, C. Chakrabarti","doi":"10.1145/1065579.1065744","DOIUrl":"https://doi.org/10.1145/1065579.1065744","url":null,"abstract":"Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time. But in a DVS system consisting of a DVS processor and multiple devices, slowing down the processor increases the device energy consumption and thereby the system-level energy consumption. In this paper, we present dynamic task scheduling algorithms for periodic tasks that minimize the system-level energy (CPU energy + device standby energy). The algorithms use a combination of (i) optimal speed setting, which is the speed that minimizes the system energy for a specific task, and (ii) limited preemption which reduces the numbers of possible preemptions. For the case when the CPU power and device power are comparable, these algorithms achieve up to 43% energy savings, but only up to 12% over the non-DVS scheduling. If the device power is large compared to the CPU power, we show that DVS should not be employed.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"34 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
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