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Proceedings. 42nd Design Automation Conference, 2005.最新文献

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Incremental exploration of the combined physical and behavioral design space 对结合物理和行为的设计空间的增量探索
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065635
Zhenyu Gu, Jia Wang, R. Dick, H. Zhou
{"title":"Incremental exploration of the combined physical and behavioral design space","authors":"Zhenyu Gu, Jia Wang, R. Dick, H. Zhou","doi":"10.1145/1065579.1065635","DOIUrl":"https://doi.org/10.1145/1065579.1065635","url":null,"abstract":"Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly important factors such as the impact of interconnect on the area and power consumption of integrated circuits. Bringing physical information up into the logic level or even behavioral-level stages of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level synthesis system. This system integrates high-level and physical design algorithms to concurrently improve a system's schedule, resource binding, and floor-plan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefit of efficiency, stability, and better quality of results. For designs containing functional units with non-unity aspect ratios, the average CPU time improved by 369 %, the area improved by 14.24 %, and power improved by 4 %.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133804904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Frequency-based code placement for embedded multiprocessors 嵌入式多处理器的基于频率的代码放置
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065762
Corey Goldfeder
{"title":"Frequency-based code placement for embedded multiprocessors","authors":"Corey Goldfeder","doi":"10.1145/1065579.1065762","DOIUrl":"https://doi.org/10.1145/1065579.1065762","url":null,"abstract":"Multiprocessor embedded systems often have processor-local caches and a shared memory. If the system's code is available at design time we can maximize cache hits by rearranging code in memory so that frequently executed tasks reside in reserved areas of the caches and are not overwritten by less frequent tasks.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122452659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High performance encryption cores for 3G networks 高性能的3G网络加密核心
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065642
T. Balderas-Contreras, R. Cumplido
{"title":"High performance encryption cores for 3G networks","authors":"T. Balderas-Contreras, R. Cumplido","doi":"10.1145/1065579.1065642","DOIUrl":"https://doi.org/10.1145/1065579.1065642","url":null,"abstract":"This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the universal mobile telecommunication system (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughputs for these architectures turn out to be higher than the throughput achieved by other proposals.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116511395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A side-channel leakage free coprocessor IC in 0.18/spl mu/m CMOS for embedded AES-based cryptographic and biometric processing 一种用于嵌入式aes密码和生物识别处理的0.18/spl mu/m CMOS侧通道无泄漏协处理器IC
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065639
K. Tiri, D. Hwang, A. Hodjat, B. Lai, Shenglin Yang, P. Schaumont, I. Verbauwhede
{"title":"A side-channel leakage free coprocessor IC in 0.18/spl mu/m CMOS for embedded AES-based cryptographic and biometric processing","authors":"K. Tiri, D. Hwang, A. Hodjat, B. Lai, Shenglin Yang, P. Schaumont, I. Verbauwhede","doi":"10.1145/1065579.1065639","DOIUrl":"https://doi.org/10.1145/1065579.1065639","url":null,"abstract":"Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18/spl mu/m CMOS. The coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an advanced encryption standard (AES) based cryptographic engine, a fingerprint-matching oracle, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, 'secure', coprocessor is implemented using a logic style called wave dynamic digital logic (WDDL) and a layout technique called differential routing. The second, 'insecure', coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"347 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116537048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 69
Mixed signal design space exploration through analog platforms 通过模拟平台探索混合信号设计空间
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065808
F. Bernardinis, P. Nuzzo, A. Sangiovanni-Vincentelli
{"title":"Mixed signal design space exploration through analog platforms","authors":"F. Bernardinis, P. Nuzzo, A. Sangiovanni-Vincentelli","doi":"10.1145/1065579.1065808","DOIUrl":"https://doi.org/10.1145/1065579.1065808","url":null,"abstract":"We propose a hierarchical mixed signal design methodology based on the principles of platform-based design (PBD). The methodology is a meet-in-the-middle approach where design components are modeled bottom-up at various abstraction levels and performance constraints are mapped top-down to select among the available components the ones that best meet the constraints. The design methodology can seamlessly operate on both analog and digital designs, thus dealing with mixed signal designs in a consistent way. We demonstrate the effectiveness of the approach optimizing an 80 MS/s 14 bit pipelined analog-to-digital converter (ADC) including digital calibration, yielding 64% power reduction compared to the original hand optimized design.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129769798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
Piece-wise approximations of RLCK circuit responses using moment matching 使用矩匹配的RLCK电路响应的分段逼近
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065822
C. Amin, Y. Ismail, F. Dartu
{"title":"Piece-wise approximations of RLCK circuit responses using moment matching","authors":"C. Amin, Y. Ismail, F. Dartu","doi":"10.1145/1065579.1065822","DOIUrl":"https://doi.org/10.1145/1065579.1065822","url":null,"abstract":"Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there is no such technique for RLCK circuits. This paper introduces a new family of MOR techniques based on piece-wise functions to capture RLCK circuit responses accurately using only four or five moments. The time-domain response is approximated using a piece-wise function whose pieces are simple polynomials. The proposed method is fast and guaranteed stable and it avoids the calculation of poles and residues associated with existing model order reduction techniques. Results for many different industrial netlists indicate that delay and transition time can be captured within 5% error using only four moments. To the authors' knowledge, there is no existing method that can extract as much information about RLCK circuits with only four or five moments.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128011325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
BEOL variability and impact on RC extraction BEOL变异及其对RC提取的影响
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065778
N. Nagaraj, T. Bonifield, Abha Singh, C. Bittlestone, U. Narasimha, Viet Le, A. Hill
{"title":"BEOL variability and impact on RC extraction","authors":"N. Nagaraj, T. Bonifield, Abha Singh, C. Bittlestone, U. Narasimha, Viet Le, A. Hill","doi":"10.1145/1065579.1065778","DOIUrl":"https://doi.org/10.1145/1065579.1065778","url":null,"abstract":"Historically, back end of line (BEOL) or interconnect resistance and capacitance have been viewed as parasitic components. They have now become key parameters with significant impact on circuit performance and signal integrity. This paper examines the types of BEOL variations and their impact on RC extraction. The importance of modeling systematic effects in RC extraction is discussed. The need for minimizing the computational error in RC extraction before incorporating random process variations is emphasized.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114314040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Asynchronous circuits transient faults sensitivity evaluation 异步电路暂态故障灵敏度评估
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065805
Y. Monnet, M. Renaudin, R. Leveugle
{"title":"Asynchronous circuits transient faults sensitivity evaluation","authors":"Y. Monnet, M. Renaudin, R. Leveugle","doi":"10.1145/1065579.1065805","DOIUrl":"https://doi.org/10.1145/1065579.1065805","url":null,"abstract":"This paper presents a transient faults sensitivity evaluation for quasi delay insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circuits have a very different behavior than synchronous circuits in the presence of faults. We address the effects of transient faults in QDI circuits and describe the causes that lead the faults to be memorized into one or more soft errors. Therefore, a refined fault sensitivity criterion is defined for this class of circuits. This methodology enables us to point out the weak parts of a circuit. An analysis tool is implemented to support this evaluation. This tool provides a quantitative study of the fault sensitivity, and enables us to compare the robustness of different architectures of a circuit along the steps of its design flow. The objective of this work is to evaluate the circuits robustness against natural faults (single fault model) and intentional fault injection (multiple faults model).","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121352576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Hybrid simulation for embedded software energy estimation 嵌入式软件能量估计的混合仿真
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065590
Anish Muttreja, A. Raghunathan, S. Ravi, N. Jha
{"title":"Hybrid simulation for embedded software energy estimation","authors":"Anish Muttreja, A. Raghunathan, S. Ravi, N. Jha","doi":"10.1145/1065579.1065590","DOIUrl":"https://doi.org/10.1145/1065579.1065590","url":null,"abstract":"Software energy estimation is a critical step in the design of energy-efficient embedded systems. Instruction-level simulation techniques, despite several advances, remain too slow for iterative use in system-level exploration. In this paper, we propose a methodology called hybrid simulation, which combines instruction set simulation with selective native execution (execution of some parts of the program directly on the simulation host computer), thereby overcoming the disadvantages of instruction-level simulation (low speed) and pure native execution (estimation accuracy, inapplicability to target-dependent code), while exploiting their advantages. Previously developed techniques for software energy macromodeling are utilized to estimate energy consumption for natively executed sub-programs. We identify and address the main challenges involved in hybrid simulation, and present an automatic tool flow for it, which analyzes a given program and selects functions for native execution in order to achieve maximum estimation efficiency while limiting estimation error. We have applied the proposed hybrid simulation methodology to a variety of embedded software programs, resulting in an average speed-up of 70% and estimation error of at most 6%, compared to one of the fastest publicly-available instruction set simulators","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126768051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Dynamic abstraction using SAT-based BMC 使用基于sat的BMC进行动态抽象
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065776
Liang Zhang, M. Prasad, M. Hsiao, Thomas Sidle
{"title":"Dynamic abstraction using SAT-based BMC","authors":"Liang Zhang, M. Prasad, M. Hsiao, Thomas Sidle","doi":"10.1145/1065579.1065776","DOIUrl":"https://doi.org/10.1145/1065579.1065776","url":null,"abstract":"We propose a new dynamic method of abstraction, which can be applied during successive steps of the model checking algorithm to further reduce the model produced by traditional static abstraction methods. This is facilitated by information gathered from an analysis of the proof of unsatisfiability of SAT-based bounded model checking problems formulated on the original design. The dynamic abstraction effectively allows the model checker to work with smaller abstract models. Experiments on several industrial benchmarks demonstrate that dynamic abstraction can significantly improve both the performance and the capacity of typical abstraction refinement flows.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"794 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123902443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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