Proceedings. 42nd Design Automation Conference, 2005.最新文献

Are there economic benefits in DFM? DFM有经济效益吗?

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065783

M. Nowak, R. Radojcic

引用次数: 7

A design platform for 90-nm leakage reduction techniques 90纳米减漏技术的设计平台

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065722

P. Royannez, H. Mair, F. Dahan, M. Wagner, M. Streeter, L. Bouetel, J. Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, C. Raibaut, U. Ko

引用次数: 2

Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation 基于高效采样灵敏度分析和分层符号松弛的电网仿真

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065753

Peng Li

{"title":"Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation","authors":"Peng Li","doi":"10.1145/1065579.1065753","DOIUrl":"https://doi.org/10.1145/1065579.1065753","url":null,"abstract":"On-chip supply networks are playing an increasingly important role for modern nanometer-scale designs. However, the ever growing sizes of power grids make the analysis problem extremely difficult thereby introducing severe challenges in design and optimization. The inherent analysis complexity calls for innovations in simulation techniques that must provide appropriate accuracy, efficiency as well as the tradeoff thereof to aid design verification and optimization. In this paper, we first present a sampling-based sensitivity analysis by employing the notation of importance sampling in a Monte Carlo based circuit simulation framework. This technique allows the extraction of multi-parameter sensitivities for the node voltages of interest in the same Monte Carlo runs that are used for computing the nominal voltage values. For more efficient nonstructured whole-grid solution approaches, we further introduce a new direct solution method by embedding symbolic relaxation steps in a hierarchical fashion. As a direct method, the proposed hierarchical symbolic relaxation is suitable to both DC and transient analyses. Circuit examples are included to demonstrate the efficacy of the proposed techniques.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"30 30","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114059444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

Structural search for RTL with predicate learning 基于谓词学习的RTL结构搜索

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065698

G. Parthasarathy, Madhu K. Iyer, K. Cheng, F. Brewer

引用次数: 9

Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration 物理感知的HW-SW分区，用于可重新配置的体系结构，具有部分动态重新配置

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065667

Sudarshan Banerjee, E. Bozorgzadeh, N. Dutt

{"title":"Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration","authors":"Sudarshan Banerjee, E. Bozorgzadeh, N. Dutt","doi":"10.1145/1065579.1065667","DOIUrl":"https://doi.org/10.1145/1065579.1065667","url":null,"abstract":"Many reconfigurable architectures offer partial dynamic configurability, but current system-level tools cannot guarantee feasible implementations when exploiting this feature. We present a physically aware hardware-software (HW-SW) scheme for minimizing application execution time under HW resource constraints, where the HW is a reconfigurable architecture with partial dynamic reconfiguration capability. Such architectures impose strict placement constraints that lead to implementation infeasibility of even optimal scheduling formulations that ignore the nature of these constraints. We propose an exact and a heuristic formulation that simultaneously partition, schedule, and do linear placement of tasks on such architectures. With our exact formulation, we prove the critical nature of placement constraints. We demonstrate that our heuristic generates high-quality schedules by comparing the results with the exact formulation for small tests and a popular, but placement-unaware scheduling heuristic for larger tests. With a case study, we demonstrate extension of our approach to handle heterogenous architectures with specialized resources distributed between general purpose programmable logic columns. The execution time of our heuristic is very reasonable - task graphs with hundreds of nodes are processed in a couple of minutes.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128465541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 109

From myth to methodology: cross-layer design for energy-efficient wireless communication 从神话到方法论:节能无线通信的跨层设计

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065659

W. Eberle, B. Bougard, S. Pollin, F. Catthoor

{"title":"From myth to methodology: cross-layer design for energy-efficient wireless communication","authors":"W. Eberle, B. Bougard, S. Pollin, F. Catthoor","doi":"10.1145/1065579.1065659","DOIUrl":"https://doi.org/10.1145/1065579.1065659","url":null,"abstract":"During the last decade, wireless communication has seen a trend towards application diversification leading to a significant growth in users. With the availability of - however energy-limited - nomadic devices and real-time multimedia applications, user demand is shifting from simply asking for higher data rates to more complex requirements in terms of quality of service (QoS) and energy-efficiency. In this new context energy management is becoming a key success factor. Optimized energy-efficiency requires an energy management that continuously trades off QoS and energy adapting to varying user expectations and environment dynamics. But, QoS can only be evaluated on top of the whole protocol stack while energy consumption largely appears at the lower layers. To minimize overhead during the transitions between layers, we need to address the problem from a cross-layer perspective. We present a methodology that, based on systematic exploration, effective problem partitioning and minimal cross-layer interface, allows energy management in a cross-layer way, while maintaining efficient layered semantics. Different case studies in the context of wireless LAN (WLAN) for multimedia and data traffic transport are discussed, to show how cross-layer energy management can easily be included in systems running state-of-the-art protocols.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128584981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Full-chip analysis of leakage power under process variations, including spatial correlations 工艺变化下的泄漏功率全芯片分析，包括空间相关性

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065716

Hongliang Chang, S. Sapatnekar

引用次数: 235

Multi-frequency wrapper design and optimization for embedded cores under average power constraints 平均功率约束下嵌入式核的多频封装设计与优化

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065615

Q. Xu, N. Nicolici, K. Chakrabarty

引用次数: 8

A combined feasibility and performance macromodel for analog circuits 模拟电路可行性与性能相结合的宏模型

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065600

Mengmeng Ding, R. Vemuri

{"title":"A combined feasibility and performance macromodel for analog circuits","authors":"Mengmeng Ding, R. Vemuri","doi":"10.1145/1065579.1065600","DOIUrl":"https://doi.org/10.1145/1065579.1065600","url":null,"abstract":"The need to reuse the performance macromodels of an analog circuit topology challenges existing regression based modeling techniques. A model of good reusability should have a number of independent design parameters and each parameter can vary in a large numeric range. On the other hand, these requirements can cause a large percentage of functionally incorrect designs in the design space and thus results in a sparse feasible design space. They also complicate the mathematical relationship between the performance parameters and the design parameters. In order to tackle these challenges, this paper presents a combined feasibility and performance macromodel based on support vector machines (SVMs). The feasibility model identifies the feasible designs that satisfy the design constraints. The performance macromodel is valid for feasible designs. Feasibility macromodeling is formulated as a classification problem while performance macromelting as a regression problem. An active learning scheme (Ding, et al., 2005) has been applied to improve the accuracy of the feasibility model much faster than only using uniformly distributed designs in the entire design space. The experiment of the authors showed that the performance macromodels in the feasible design space are more accurate and faster to construct and evaluate than performance macromodels in the entire design space without functional or performance constraints considered.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121133962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

Can we really do without the support of formal methods in the verification of large designs? 在大型设计的验证中，我们真的可以没有形式化方法的支持吗?

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065756

U. Rossi

引用次数: 1