Multi-frequency wrapper design and optimization for embedded cores under average power constraints

Abstract

This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed method improves upon a recent wrapper design method that requires a common shift frequency for the scan elements in the different clock domains. The authors presented an integer linear programming (ILP) model that could be used to minimize the testing time for small problem instances. An efficient heuristic method that is applicable to large problem instances, and which yields the same (optimal) testing time as ILP for small problem instances was also presented. Compared to recent work on wrapper design using a single shift frequency, lower testing times were obtained and the reduction in testing time is especially significant under power constraints.