Proceedings. 42nd Design Automation Conference, 2005.最新文献_第10页

DC-DC converter-aware power management for battery-operated embedded systems 电池供电嵌入式系统的DC-DC转换器感知电源管理

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065814

Yongseok Choi, N. Chang, Taewhan Kim

{"title":"DC-DC converter-aware power management for battery-operated embedded systems","authors":"Yongseok Choi, N. Chang, Taewhan Kim","doi":"10.1145/1065579.1065814","DOIUrl":"https://doi.org/10.1145/1065579.1065814","url":null,"abstract":"Most digital systems are equipped with DC-DC converters to supply various levels of voltages from batteries to logic devices. DC-DC converters maintain legal voltage ranges regardless of the load current variation as well as battery voltage drop. Although the efficiency of DC-DC converters is changed by the output voltage level and the load current, most existing power management techniques simply ignore the efficiency variation of DC-DC converters. However, without a careful consideration of the efficiency variation of DC-DC converters, finding a true optimal power management is impossible. In this work, we solve the problem of energy minimization with the consideration of the characteristics of power consumption of DC-DC converter. Specifically, the contributions of our work are: (1) We analyze the effects of the efficiency variation of DC-DC converters on a single task execution in DVS (dynamic voltage scaling) scheme, and propose a technique, called DC/spl I.bar/DVS, of DC-DC converter-aware energy-minimal DVS; (2) DC/spl I.bar/DVS is then extended to combine the effects of DC-DC converters with the procedures of general DVS techniques with multiple tasks; (3) Conversely, we propose a technique, called DC/spl I.bar/CONF, of generating a DC-DC converter that is best suited, in terms of total energy efficiency, to the intended application, and (4) finally, we complete our integrated framework DC-lp, which is based on DC/spl I.bar/DVS and DC/spl I.bar/CONF, that attempts to solve the DC-DC converter configuration selection problem and the DVS problem simultaneously. To show the effectiveness of the proposed techniques, a set of experimental results is provided. In summary, it is shown that DC-lp is able to save 16.0% /spl sim/ 22.1% of energy on the average, which otherwise was dissipated in the previous power management schemes with no consideration of DC-DC converter efficiency variation.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121602075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 27

Self-compensating design for focus variation 自补偿设计的焦点变化

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065677

Puneet Gupta, A. Kahng, Youngmin Kim, D. Sylvester

{"title":"Self-compensating design for focus variation","authors":"Puneet Gupta, A. Kahng, Youngmin Kim, D. Sylvester","doi":"10.1145/1065579.1065677","DOIUrl":"https://doi.org/10.1145/1065579.1065677","url":null,"abstract":"Process variations have become a bottleneck for predictable and high-yielding IC design and fabrication. Linewidth variation (/spl Delta/L) due to defocus in a chip is largely systematic after the layout is completed, i.e., dense lines \"smile\" through focus while isolated (iso) lines \"frown\". In this paper, we propose a design flow that allows explicit compensation of focus variation, either within a cell (self-compensated cells) or across cells in a critical path (self-compensated design). Assuming that iso and dense variants are available for each library cell, we achieve designs that are more robust to focus variation. Design with a self-compensated cell library incurs /spl sim/11-12% area penalty while compensating for focus variation. Across-cell optimization with a mix of dense and iso cell variants incurs /spl sim/6-8% area overhead compared to the original cell library, while meeting timing constraints across a large range of focus variation (from 0 to 0.4/spl mu/m). A combination of original and iso cells provides an even better self-compensating design option, with only 1% area overhead. Circuit delay distributions are tighter with self-compensated cells and self-compensated design than with a conventional design methodology.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115161883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Cognitive radio techniques for wide area networks 广域网认知无线电技术

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065688

W. Krenik, A. Batra

引用次数: 111

Microarchitecture-aware floorplanning using a statistical design of experiments approach 使用统计设计实验方法的微架构感知地板规划

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065731

Vidyasagar Nookala, Ying Chen, D. Lilja, S. Sapatnekar

{"title":"Microarchitecture-aware floorplanning using a statistical design of experiments approach","authors":"Vidyasagar Nookala, Ying Chen, D. Lilja, S. Sapatnekar","doi":"10.1145/1065579.1065731","DOIUrl":"https://doi.org/10.1145/1065579.1065731","url":null,"abstract":"Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi-cycle delays. Although such a wire pipelining strategy allows higher operating frequencies, it can reduce the delivered performance of a microarchitecture, since the extra flip-flops inserted may increase the operation latencies and stall cycles. Moreover, the addition of latencies on some wires can have a large impact on the overall performance while other wires are relatively insensitive to additional latencies. This varying sensitivity suggests the need for a throughput-aware strategy for pipelining the interconnects that interacts closely with the physical design step, which determines the lengths of these multicycle wires. We use a statistical design of experiments strategy based on a multifactorial design, which intelligently uses a limited number of simulations to rank the importance of the wires. When applied at the floorplanning level, our results show improvements both in the overall system performance and in the total wire length when compared with an existing technique.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128938646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 39

Hardware speech recognition for user interfaces in low cost, low power devices 用于低成本、低功耗设备的用户界面的硬件语音识别

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065760

S. Nedevschi, Rabin K. Patra, E. Brewer

{"title":"Hardware speech recognition for user interfaces in low cost, low power devices","authors":"S. Nedevschi, Rabin K. Patra, E. Brewer","doi":"10.1145/1065579.1065760","DOIUrl":"https://doi.org/10.1145/1065579.1065760","url":null,"abstract":"We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user interfaces as part of an effort to bring information and communication technologies (ICTs) to underdeveloped regions of the world. Our system architecture exploits a shared infrastructure model. The computationally intensive task of speech model training and retraining is performed offline by shared servers, while the actual recognition of speech is conducted on low-cost hand-held devices using custom hardware. The recognizer is extremely flexible and can support multiple languages or dialects with speaker-independent recognition. Dynamic loading of speech models is used for changing language grammar and retraining, while reprogramming is used to support evolution of recognition algorithms. The focus on small sets of words (at one time) reduces the complexity, cost and power consumption. We design the speech decoder, the central component of the recognizer, and we validate it via a prototype FPGA implementation. We then use ASIC synthesis to estimate power and size for the design. Our evaluations demonstrate an order of magnitude improvement in power compared with optimized recognition software running on a low-power embedded general-purpose processor of the same technology and of similar capabilities. The synthesis also estimates the area of the design to be about 2.5mm, showing potential for lower cost. In designing and testing our recognizer we use datasets in both English and Tamil languages.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127566967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

Application/architecture power co-optimization for embedded systems powered by renewable sources 面向可再生能源驱动的嵌入式系统的应用/架构功耗协同优化

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065742

Dexin Li, P. Chou

引用次数: 11

N-detection under transparent-scan 透明扫描下的n检测

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065616

I. Pomeranz

引用次数: 1

Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits 跟踪保持电路和采样保持电路中时序抖动影响的仿真

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065685

V. Vasudevan

引用次数: 5

Beyond safety: customized SAT-based model checking 超越安全:定制的基于sat的模型检查

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065773

Malay K. Ganai, Aarti Gupta, P. Ashar

{"title":"Beyond safety: customized SAT-based model checking","authors":"Malay K. Ganai, Aarti Gupta, P. Ashar","doi":"10.1145/1065579.1065773","DOIUrl":"https://doi.org/10.1145/1065579.1065773","url":null,"abstract":"Model checking of safety properties has taken a significant lead over nonsafety properties in recent years. To bridge the gap, we propose dedicated SAT-based model checking algorithms for properties beyond safety. Previous bounded model checking (BMC) approaches have relied on either converting such properties to safety checking, or finding proofs by deriving termination criteria using loop-free path analysis. Instead, our approach uses a customized SAT-based formulation for bounded model checking of nonsafety properties, and determines the completeness bounds for liveness using unbounded SAT-based analysis. Our main contributions are: 1) Customized property translations for LTL formulas for BMC, with novel features that utilize partitioning, learning, and incremental formulation. Customized translations not only improve the BMC performance significantly in comparison to standard monolithic LTL translations, but also allow efficient derivation and use of completeness bounds. Though we discuss the translation schemas for liveness, they can be easily extended to handle other LTL properties as well. 2) Customized formulations for determining completeness bounds for liveness using SAT-based unbounded model checking (UMC) rather than using loop-free path analysis. These formulations comprise greatest fixed-point and least fixed-point computations to efficiently handle nested properties using SAT-based quantification approaches. We show the effectiveness of our overall approach for checking liveness on public benchmarks and several industry designs.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116690053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Energy-efficient physically tagged caches for embedded processors with virtual memory 具有虚拟内存的嵌入式处理器的节能物理标记缓存

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065589

Peter Petrov, Daniel J. Tracy, A. Orailoglu

{"title":"Energy-efficient physically tagged caches for embedded processors with virtual memory","authors":"Peter Petrov, Daniel J. Tracy, A. Orailoglu","doi":"10.1145/1065579.1065589","DOIUrl":"https://doi.org/10.1145/1065579.1065589","url":null,"abstract":"In this paper we present a low-power tag organization for physically tagged caches in embedded processors with virtual memory support. An exceedingly small subset of tag bits is identified for each application hot-spot so that only these tag bits are used for cache access with no performance sacrifice as they provide complete address resolution. The minimal subset of physical tag bits, i.e. the compressed tag, is dynamically updated following the changes in the physical address space of the application. Special support from the operating system (OS) is introduced in order to maintain the compressed tag during program execution. The compressed tag is updated by the OS to match the current set of physical memory pages allocated to the application. We have proposed efficient algorithms that are incorporated within the memory allocator and the dynamic linker in order to achieve dynamic update of the compressed tags in the cases where the mapping between virtual and physical addresses is modified; such cases include memory allocation/deallocation and swapping physical pages on the secondary memory storage. The only hardware support needed within the l/D-caches is the support for disabling bitlines of the tag arrays. An extensive set of experimental results demonstrates the efficacy of the proposed approach.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116576198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7