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Proceedings. 42nd Design Automation Conference, 2005.最新文献

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Analysis of full-wave conductor system impedance over substrate using novel integration techniques 利用新型集成技术分析衬底上的全波导体系统阻抗
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065620
Xin Hu, Jung Hoon Lee, Jacob K. White, L. Daniel
{"title":"Analysis of full-wave conductor system impedance over substrate using novel integration techniques","authors":"Xin Hu, Jung Hoon Lee, Jacob K. White, L. Daniel","doi":"10.1145/1065579.1065620","DOIUrl":"https://doi.org/10.1145/1065579.1065620","url":null,"abstract":"An efficient approach to full-wave impedance extraction is developed that accounts for substrate effects through the use of two-layer media Green's functions in a mixed-potential-integral-equation (MPIE) solver. Particularly, the choice of implementation for the layered media Green's functions motivates the development of accelerated techniques for both volume and surface integrations in the solver. Solver accuracy is validated against measurements taken on fabricated devices; solver efficiency is demonstrated by its 9.8/spl times/ reduction in cost in comparison to the traditional integration approach.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127962764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 /spl mu/m and 90nm technologies 0.13 /spl mu/m和90nm技术在SRAM核心细胞中的阻性开放缺陷注射分析与比较
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065804
L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian
{"title":"Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 /spl mu/m and 90nm technologies","authors":"L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, M. Bastian","doi":"10.1145/1065579.1065804","DOIUrl":"https://doi.org/10.1145/1065579.1065804","url":null,"abstract":"Resistive-open defects appear more and more frequently in VDSM technologies. In this paper we present a study concerning resistive-open defects in the core-cell of SRAM memories. The first target of this work is a comparison of the effect produced by resistive-open defects in the 0.13 /spl mu/m and 90 nm core-cell. We show that the 90 nm core-cell is more robust than the 0.13/spl mu/ m core-cell in presence of resistive-open defects. On the other hand we show that dynamic faults are most likely to occur in the 90 nm than in 0.13 /spl mu/m core-cell. Finally we propose a unique March test solution that ensures the complete coverage of all the extracted fault models for both technologies.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121169824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits 约束感知鲁棒性插入在VLSI电路中优化容噪能力
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065631
Chong Zhao, Yi Zhao, S. Dey
{"title":"Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits","authors":"Chong Zhao, Yi Zhao, S. Dey","doi":"10.1145/1065579.1065631","DOIUrl":"https://doi.org/10.1145/1065579.1065631","url":null,"abstract":"Reliability of nanometer circuits is becoming a major concern in today's VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft errors. Traditional noise analysis/avoidance and manufacturing testing are no longer sufficient to handle the dynamic interactions between various noise sources and unpredictable operational variations. Therefore, \"robustness insertion\" has been adopted as the supplementary approach to ensure high circuit reliability through on-line protections. However, the related design overhead is not always acceptable, especially for cost/timing-sensitive designs. In this paper, we present a novel \"constraint-aware robustness insertion\" methodology protect the sequential elements in digital circuits against various noise effects. Based on a configurable hardening sequential cell design and an efficient sequential cell robustness estimation technique, an optimization algorithm is developed to search for the optimal protection scheme under given timing and area constraints. Experiment results demonstrate that the proposed methodology is able to achieve a high degree of noise-tolerance while keeping the protection cost within limit.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123265466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A low latency router supporting adaptivity for on-chip interconnects 支持片上互连的适应性的低延迟路由器
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065726
Jongman Kim, Dongkook Park, T. Theocharides, N. Vijaykrishnan, C. Das
{"title":"A low latency router supporting adaptivity for on-chip interconnects","authors":"Jongman Kim, Dongkook Park, T. Theocharides, N. Vijaykrishnan, C. Das","doi":"10.1145/1065579.1065726","DOIUrl":"https://doi.org/10.1145/1065579.1065726","url":null,"abstract":"The increased deployment of system-on-chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, networks-on-chip (NoC) have been proposed. The NoC routing algorithm significantly influences the performance and energy consumption of the chip. We propose a router architecture which utilizes adaptive routing while maintaining low latency. The two-stage pipelined architecture uses look ahead routing, speculative allocation, and optimal output path selection concurrently. The routing algorithm benefits from congestion-aware flow control, making better routing decisions. We simulate and evaluate the proposed architecture in terms of network latency and energy consumption. Our results indicate that the architecture is effective in balancing the performance and energy of NoC designs.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124016115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 266
Faster and better global placement by a new transportation algorithm 通过新的运输算法实现更快更好的全局布局
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065733
Ulrich Brenner, Markus Struzyna
{"title":"Faster and better global placement by a new transportation algorithm","authors":"Ulrich Brenner, Markus Struzyna","doi":"10.1145/1065579.1065733","DOIUrl":"https://doi.org/10.1145/1065579.1065733","url":null,"abstract":"We present BonnPlace, a new VLSI placement algorithm that combines the advantages of analytical and partitioning-based placers. Based on (non-disjoint) placements minimizing the total quadratic netlength, we partition the chip area into regions and assign the circuits to them (meeting capacity constraints) such that the placement is changed as little as possible. The core routine of our placer is a new algorithm for the transportation problem that allows to compute efficiently the circuit assignments to the regions. We test our algorithm on a set of industrial designs with up to 3.6 millions of movable objects and two sets of artificial benchmarks showing that it produces excellent results. In terms of wirelength, we can improve the results of leading-edge placement tools by about 5%.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123024662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems 实时嵌入式系统中带有延迟调度的动态空闲回收
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065612
R. Jejurikar, Rajesh K. Gupta
{"title":"Dynamic slack reclamation with procrastination scheduling in real-time embedded systems","authors":"R. Jejurikar, Rajesh K. Gupta","doi":"10.1145/1065579.1065612","DOIUrl":"https://doi.org/10.1145/1065579.1065612","url":null,"abstract":"Leakage energy consumption is an increasing concern in current and future CMOS technology generations. Procrastination scheduling, where task execution can be delayed to maximize the duration of idle intervals, has been proposed to minimize leakage energy drain. The authors addressed dynamic slack reclamation techniques under procrastination scheduling to minimize the static and dynamic energy consumption. In addition to dynamic task slowdown, a dynamic procrastination was proposed, which seeks to extend idle intervals through slack reclamation. While using the entire slack for either slowdown or procrastination need not be the most energy efficient approach, the slack was distributed between slowdown and procrastination to exploit maximum energy savings. The simulation experiments showed that dynamic slowdown result on an average 10% energy gains over static slowdown. Dynamic procrastination extends the average sleep interval by 25%, which reduces the idle energy consumption by 15%, while meeting all timing requirements.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1992 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128611789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 170
Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips 统一的高级合成和模块放置的缺陷容忍微流控生物芯片
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065797
Fei Su, K. Chakrabarty
{"title":"Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips","authors":"Fei Su, K. Chakrabarty","doi":"10.1145/1065579.1065797","DOIUrl":"https://doi.org/10.1145/1065579.1065797","url":null,"abstract":"Microfluidic biochips promise to revolutionize biosensing and clinical diagnostics. As more bioassays are executed concurrently on a biochip, system integration and design complexity are expected to increase dramatically. This problem is also identified by the 2003 ITRS document as a major system-level design challenge beyond 2009. We focus here on the automated design of droplet-based microfluidic biochips. We present a synthesis methodology that unifies operation scheduling, resource binding, and module placement for such \"digital\" biochips. The proposed technique, which is based on parallel recombinative simulated annealing, can also be used after fabrication to bypass defective cells in the microfluidic array. A real-life protein assay is used to evaluate the synthesis methodology.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127010992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 154
Net weighting to reduce repeater counts during placement 净加权，以减少重复器计数在放置期间
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065710
B. Goplen, Prashant Saxena, S. Sapatnekar
{"title":"Net weighting to reduce repeater counts during placement","authors":"B. Goplen, Prashant Saxena, S. Sapatnekar","doi":"10.1145/1065579.1065710","DOIUrl":"https://doi.org/10.1145/1065579.1065710","url":null,"abstract":"We demonstrate how to use placement to ameliorate the predicted repeater explosion problem caused by poor interconnect scaling. We achieve repeater count reduction by dynamically modifying net weights in a context-sensitive manner during global placement and coarse legalization. Our scheme, which models layer assignment as well as valid inter-repeater distance ranges, can decrease the repeater counts significantly with minimal impact on wirelength.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116946880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Simulation models for side-channel information leaks 边信道信息泄漏仿真模型
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065640
K. Tiri, I. Verbauwhede
{"title":"Simulation models for side-channel information leaks","authors":"K. Tiri, I. Verbauwhede","doi":"10.1145/1065579.1065640","DOIUrl":"https://doi.org/10.1145/1065579.1065640","url":null,"abstract":"Small, embedded integrated circuits (ICs) such as smart cards are vulnerable to so-called side-channel attacks (SCAs). The attacker can gain information by monitoring the power consumption, execution time, electromagnetic radiation and other information that is leaked by the switching behavior of digital CMOS gates. Ever since power attacks have been introduced in 1999, many countermeasures have been proposed. Often a significant increase in security has been touted. We will show that in order to assess the effectiveness of a countermeasure, a correct simulation model of the side-channel information leaks is vital. We will show that seemingly correct approximations can lead to completely flawed results.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123923120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
A 24 GHz phased-array transmitter in 0.18/spl mu/m CMOS 一个24 GHz相控阵发射机在0.18/spl mu/m CMOS
Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065723
A. Natarajan, A. Komijani, A. Hajimiri
{"title":"A 24 GHz phased-array transmitter in 0.18/spl mu/m CMOS","authors":"A. Natarajan, A. Komijani, A. Hajimiri","doi":"10.1145/1065579.1065723","DOIUrl":"https://doi.org/10.1145/1065579.1065723","url":null,"abstract":"A fully-integrated 4-element phased array transmitter at 24 GHz with on-chip PAs is demonstrated in 0.18/spl mu/m CMOS. It has a beam-forming resolution of 10/spl deg/, a peak-to-null ratio of 23 dB, and 28 dB isolation between paths. Each PA can deliver up to +14 dBm into 50 /spl Omega/ in saturation. The die size is 6.8mm /spl times/ 2.1mm. The transmitter bandwidth is more than 400MHz and supports up to 1Gbit/s QPSK, facilitating a gigabit wireless LAN solution.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124333758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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