Proceedings. 42nd Design Automation Conference, 2005.最新文献_第2页

Design methodology for IC manufacturability based on regular logic-bricks 基于规则逻辑块的集成电路可制造性设计方法

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065675

V. Kheterpal, V. Rovner, Thiago Hersan, D. Motiani, Y. Takegawa, A. Strojwas, Larry Pileggi

{"title":"Design methodology for IC manufacturability based on regular logic-bricks","authors":"V. Kheterpal, V. Rovner, Thiago Hersan, D. Motiani, Y. Takegawa, A. Strojwas, Larry Pileggi","doi":"10.1145/1065579.1065675","DOIUrl":"https://doi.org/10.1145/1065579.1065675","url":null,"abstract":"Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry patterns (Palusinski et al., 2001 and Strojwas, 2003) can provide significant advantages in terms of manufacturability and design cost (Pileggi et al., 2003). Various forms of gate and logic arrays have been recently proposed that can offer such pattern regularity to reduce design risk and costs. In this paper, we propose a full-mask-set design methodology which provides the same physical design coherence as a configurable array, but with area and other design benefits comparable to standard cell ASICs. This methodology is based on a set of simple logic primitives that are mapped to a set of logic bricks that are defined by a restrictive set of RET (resolution enhancement technique)-friendly geometry patterns. We propose a design methodology to explore trade-offs between the number of bricks and associated level of configurability versus the required silicon area. Results are shown to compare a design implemented with a small number of regular bricks to an implementation based on a full standard cell library in a 90nm CMOS technology.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"139 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115890856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 103

A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents 一种通过监测泄漏电流来确定最佳RBB的自调节方案

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065595

N. Jayakumar, S. Dhar, S. Khatri

引用次数: 11

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs 温度表编码电流转向dac诊断和过程变化感知结构测试的DFT方法

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065803

R. Topaloglu, A. Orailoglu

{"title":"A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs","authors":"R. Topaloglu, A. Orailoglu","doi":"10.1145/1065579.1065803","DOIUrl":"https://doi.org/10.1145/1065579.1065803","url":null,"abstract":"A design for test (DFT) hardware is proposed to increase the controllability of a thermometer coded current steering digital to analog converter. A procedure is introduced to reduce the diagnosis and structural test time from quadratic to linear using the proposed DFT hardware. To evaluate the applicability of the proposed technique, principal component analysis is used to create virtual process variations to simulate in lieu of semiconductor fabrication data. An architecture specific soft fault model is suggested for the diagnosis problem. Random errors according to the fault model are introduced in the virtual test environment on top of the process variations and it is shown that diagnosis of a fault is possible with high accuracy with the proposed method. The same technique employing principal component analysis is furthermore used to provide process variation-aware reference test comparison values for a structural test of the DAC. The structural test provides a mechanism to test for even unmodeled manufacturing faults. The process variation-aware test values help detect defects even under process variations. The proposed DFT hardware and method are low cost and quite suitable for a built-in self diagnosis and test implementation.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117318474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Robust gate sizing by geometric programming 基于几何规划的稳健闸门尺寸确定

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065662

Jaskirat Singh, Vidyasagar Nookala, Z. Luo, S. Sapatnekar

{"title":"Robust gate sizing by geometric programming","authors":"Jaskirat Singh, Vidyasagar Nookala, Z. Luo, S. Sapatnekar","doi":"10.1145/1065579.1065662","DOIUrl":"https://doi.org/10.1145/1065579.1065662","url":null,"abstract":"We present an efficient optimization scheme for gate sizing in the presence of process variations. Using a posynomial delay model, the delay constraints are modified to incorporate uncertainty in the transistor widths and effective channel lengths due to the process variations. An uncertainty ellipsoid method is used to model the random parameter variations. Spatial correlations of intra-die width and channel length variations are incorporated in the optimization procedure. The resulting optimization problem is relaxed to be a geometric program and is efficiently solved using convex optimization tools. The effectiveness of our robust gate sizing scheme is demonstrated by applying the optimization on the ISCAS '85 benchmark circuits and testing the optimized circuits by performing Monte Carlo simulations to model the process variations. By varying the size of the uncertainty ellipsoids, a trade-off between area and robustness is explored. Experimental results show that the timing yield of the robustly optimized circuits improves manifold over the traditional deterministically sized circuits. As compared to the worst-case design, the robust gate sizing solution having the same area has fewer timing violations.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131216382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 130

Diffusion-based placement migration 基于扩散的安置迁移

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065712

Haoxing Ren, D. Pan, C. Alpert, P. Villarrubia

引用次数: 66

Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs 异构mpsoc上非共享总线架构的缓存一致性支持

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065725

Taeweon Suh, Daehyun Kim, H. Lee

引用次数: 10

Partitioning-based approach to fast on-chip decap budgeting and minimization 基于分区的快速片上封装预算和最小化方法

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065627

Hang Li, Z. Qi, S. Tan, Lifeng Wu, Yici Cai, Xianlong Hong

{"title":"Partitioning-based approach to fast on-chip decap budgeting and minimization","authors":"Hang Li, Z. Qi, S. Tan, Lifeng Wu, Yici Cai, Xianlong Hong","doi":"10.1145/1065579.1065627","DOIUrl":"https://doi.org/10.1145/1065579.1065627","url":null,"abstract":"This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today's VLSI physical design. The new method is based on a sensitivity-based conjugate gradient (CG) approach. But it adopts several new techniques, which significantly improve the efficiency of the optimization process. First, the new approach applies the time-domain merged adjoint network method for fast sensitivity calculation. Second, an efficient search step scheme is proposed to replace the time-consuming line search phase in conventional conjugate gradient method for decap budget optimization. Third, instead of optimizing an entire large circuit, we partition the circuit into a number of smaller sub-circuits and optimize them separately by exploiting the locality of adding decaps. Experimental results show that the proposed algorithm achieves at least 10X speed-up over the fastest decap allocation method reported so far with similar or even better budget quality and a power grid circuit with about one million nodes can be optimized using the new method in half an hour on the latest Linux workstations.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"166 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 48

Mapping statistical process variations toward circuit performance variability: an analytical modeling approach 对电路性能变异性的统计过程变化映射:一种分析建模方法

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065752

Yu Cao, L. Clark

引用次数: 181

Implementing low-power configurable processors - practical options and tradeoffs 实现低功耗可配置处理器——实用的选择和权衡

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065765

J. Wei, C. Rowen

{"title":"Implementing low-power configurable processors - practical options and tradeoffs","authors":"J. Wei, C. Rowen","doi":"10.1145/1065579.1065765","DOIUrl":"https://doi.org/10.1145/1065579.1065765","url":null,"abstract":"Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors. This energy advantage comes from three improvements. First, configuration of the instruction set permits a much closer fit of the processor to the target applications, reducing the number of execution cycles required. Second, configuring the processor removes unneeded features, reducing power and area overhead. Third, automatic processor generation tools enable logic optimization, signal switching reductions, and seamless mapping into low-voltage circuits and processes, for very low-power operation. The first improvement has been well-studied. Analysis of the second and third improvements requires detailed circuit and layout experiments, which is the primary focus of this paper. Starting from a range of existing available power saving options, this work explores the tradeoff and analyzes the results: the design priority tradeoff, the process technology impact, and implementing low-power configurable processor using commercial scaled-VDD cell libraries compatible with mainstream SOC practices. These real processor designs can achieve power dissipation approaching 20/spl mu/W/MHz at 0.8V and close to 10/spl mu/W/MHz at 0.6V, using production 0.13/spl mu/m libraries. Finally, this work quantifies the dramatic process, voltage and temperature dependence in post-layout leakage power for small processor designs.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115212233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Incremental retiming for FPGA physical synthesis FPGA物理合成的增量重定时

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065694

Deshanand P. Singh, Valavan Manohararajah, S. Brown

引用次数: 34