Proceedings. 42nd Design Automation Conference, 2005.最新文献_第7页

Exploiting suspected redundancy without proving it 利用可疑的冗余而不证明它

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065700

Hari Mony, J. Baumgartner, Viresh Paruthi, Robert Kanzelman

引用次数: 44

SEU tolerant device, circuit and processor design 容错器件、电路和处理器的设计

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065586

W. Heidergott

引用次数: 29

Matlab as a development environment for FPGA design 以Matlab为开发环境进行FPGA设计

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065737

Tejas M. Bhatt, D. McCain

引用次数: 17

Optimal procrastinating voltage scheduling for hard real-time systems 硬实时系统的最优延迟电压调度

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065816

Yan Zhang, Zhijian Lu, J. Lach, K. Skadron, M. Stan

引用次数: 36

Path delay test compaction with process variation tolerance 具有工艺变化公差的路径延迟测试压实

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065802

S. Kajihara, Masayasu Fukunaga, X. Wen, T. Maeda, S. Hamada, Yasuo Sato

引用次数: 12

Locality-conscious workload assignment for array-based computations in MPSOC architectures MPSOC架构中基于阵列计算的位置感知工作负载分配

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065609

Feihui Li, M. Kandemir

{"title":"Locality-conscious workload assignment for array-based computations in MPSOC architectures","authors":"Feihui Li, M. Kandemir","doi":"10.1145/1065579.1065609","DOIUrl":"https://doi.org/10.1145/1065579.1065609","url":null,"abstract":"While the past research discussed several advantages of multiprocessor-system-on-a-chip (MPSOC) architectures from both area utilization and design verification perspectives over complex single core based systems, compilation issues for these architectures have relatively received less attention. Programming MPSOCs can be challenging as several potentially conflicting issues such as data locality, parallelism and load balance across processors should be considered simultaneously. Most of the compilation techniques discussed in the literature for parallel architectures (not necessarily for MPSOCs) are loop based, i.e., they consider each loop nest in isolation. However, one key problem associated with such loop based techniques is that they fail to capture the interactions between the different loop nests in the application. This paper takes a more global approach to the problem and proposes a compiler-driven data locality optimization strategy in the context of embedded MPSOCs. An important characteristic of the proposed approach is that, in deciding the workloads of the processors (i.e., in parallelizing the application) it considers all the loop nests in the application simultaneously. The authors' experimental evaluation with eight embedded applications showed that the global scheme brings significant power/performance benefits over the conventional loop based scheme.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130673489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis 基于快速嵌入噪声规则计算的功能噪声驱动有效电容法

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065630

Haihua Su, D. Widiger, Chandramouli V. Kashyap, Frank Liu, B. Krauter

{"title":"A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis","authors":"Haihua Su, D. Widiger, Chandramouli V. Kashyap, Frank Liu, B. Krauter","doi":"10.1145/1065579.1065630","DOIUrl":"https://doi.org/10.1145/1065579.1065630","url":null,"abstract":"We present a noise-driven effective capacitance method for estimating the combined propagation noise and crosstalk noise. Gate propagation noise rules are efficiently calculated inside the Ceff procedure to determine a linear Thevenin model of the victim driver. A voltage-dependent current source model (Croix and Wong, 2003 and Keller et al.,2004) of the driver, along with a load capacitor is analyzed to generate the gate output waveform, from which noise rules are directly extracted. This method removes potential errors introduced in traditional look-up table or fitted-equation based noise rules. The linear driver Thevenin model can then be employed to analyze the propagation noise, while the same Thevenin resistance can be used to analyze the crosstalk noise. The combined coupling and propagation noise can then be estimated using superposition. In this work, we extend the popular timing-driven effective capacitance method into the noise domain. Similar to the effective capacitance method in timing analysis, this technique can successfully separate the nonlinear driver analysis from the linear interconnect analysis. In addition, the linear driver model can significantly ease the task of finding the worst-case peak alignment among all the victim and aggressor noise sources. Experimental results on both RC and RLC nets from industry designs show both accuracy and efficiency compared to SPICE results.","PeriodicalId":397347,"journal":{"name":"Proceedings. 42nd Design Automation Conference, 2005.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133499729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Multi-level approach for integrated spiral inductor optimization 集成螺旋电感优化的多级方法

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065749

A. Nieuwoudt, Y. Massoud

引用次数: 71

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance 考虑泄漏功率和性能相关变化的准确有效的门级参数屈服估计

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065718

A. Srivastava, Saumil Shah, K. Agarwal, D. Sylvester, D. Blaauw, S. W. Director

引用次数: 95

Statistical static timing analysis: how simple can we get? 统计静态定时分析:我们能得到多简单?

Proceedings. 42nd Design Automation Conference, 2005. Pub Date : 2005-06-13 DOI: 10.1145/1065579.1065751

C. Amin, N. Menezes, Kip Killpack, F. Dartu, U. Choudhury, N. Hakim, Y. Ismail

引用次数: 107