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Third International ACM Symposium on Field-Programmable Gate Arrays最新文献

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Multi-Way System Partitioning into a Single Type or Multiple Types of FPGAs 多路系统划分为单一类型或多个类型的fpga
Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201332
D. J. Huang, A. Kahng
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引用次数: 28
High-Energy Physics on DECPeRLe-1 Programmable Active Memory DECPeRLe-1可编程主动存储器的高能物理
Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201318
L. Moll, J. Vuillemin, P. Boucard
{"title":"High-Energy Physics on DECPeRLe-1 Programmable Active Memory","authors":"L. Moll, J. Vuillemin, P. Boucard","doi":"10.1145/201310.201318","DOIUrl":"https://doi.org/10.1145/201310.201318","url":null,"abstract":"The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126452940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping 基于lut的FPGA技术映射中的标称时延最小化
Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1994-12-01 DOI: 10.1145/201310.201324
J. Cong, Y. Ding
{"title":"On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping","authors":"J. Cong, Y. Ding","doi":"10.1145/201310.201324","DOIUrl":"https://doi.org/10.1145/201310.201324","url":null,"abstract":"We study the nominal delay minimization problemin LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3, and remains NP-hard for duplication-free mapping and tree-based mapping for K ≥ 5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123239225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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