On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping

Abstract

We study the nominal delay minimization problemin LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3, and remains NP-hard for duplication-free mapping and tree-based mapping for K ≥ 5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.