Third International ACM Symposium on Field-Programmable Gate Arrays最新文献

The Design of RPM: An FPGA-based Multiprocessor Emulator 基于fpga的多处理器仿真器RPM的设计

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201321

Koray Öner, L. Barroso, S. Iman, Jaeheon Jeong, Krishnan Ramamurthy, M. Dubois

引用次数: 31

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs 松弛邻域图在fpga时序驱动优化问题中的应用

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201329

Anmol Mathur, Kuang-Chien Chen, C. Liu

引用次数: 6

A Field-Programmable Mixed-Analog-Digital Array 一种现场可编程混合模拟-数字阵列

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201327

P. Chow, P. Gulak

引用次数: 33

Techniques for FPGA Implementation of Video Compression Systems 视频压缩系统的FPGA实现技术

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201334

B. Schoner, J. Villasenor, S. Molloy, R. Jain

引用次数: 30

TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation 层:拓扑无关的流水线路由和调度的VirtualWire&#8482编译

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201314

C. Selvidge, A. Agarwal, M. Dahl, J. Babb

引用次数: 39

Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping 基于lut的FPGA映射的同时深度和面积最小化

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201322

J. Cong, Yean-Yow Hwang

引用次数: 102

High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems 多fpga系统的高级位串行数据路径合成

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201336

T. Isshiki, W. Dai

引用次数: 23

Multiple FPGA Partitioning with Performance Optimization 性能优化的多FPGA分区

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201333

Kalapi Roy-Neogi, C. Sechen

{"title":"Multiple FPGA Partitioning with Performance Optimization","authors":"Kalapi Roy-Neogi, C. Sechen","doi":"10.1145/201310.201333","DOIUrl":"https://doi.org/10.1145/201310.201333","url":null,"abstract":"We address the problem of partitioning a technology mapped FPGA circuit onto multiple FPGAs of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre-designed interconnection patterns of the MFS. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a rectilinear partitioning algorithm which efficiently and accurately handles timing specifications. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. A new dynamic net-weighting scheme was incorporated to minimize the number of pin-outs for each chip. Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure. We successfully partitioned the MCNC Xilinx FPGA benchmarks producing 100% routable designs with high utilization levels in all cases. Using the performance optimization capabilities in our approach we have successfully partitioned these benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17% in the longest path delay was achieved at the cost of 5% in total wire length. We have proved the effectiveness of our performance optimization technique by verifying the timing predictions of our partitioner with the actual delays obtained after placement and routing of a partitioned MFS. Partitioning results obtained with the Xilinx mapped MCNC benchmarks are encouraging.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134381169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 42

Using Architectural "Families" to Increase FPGA Speed and Density 利用架构“家族”提高FPGA速度和密度

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201312

Vaughn Betz, Jonathan Rose

引用次数: 13

HGA: A Hardware-Based Genetic Algorithm HGA:基于硬件的遗传算法

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201319

S. Scott, A. Samal, S. Seth

{"title":"HGA: A Hardware-Based Genetic Algorithm","authors":"S. Scott, A. Samal, S. Seth","doi":"10.1145/201310.201319","DOIUrl":"https://doi.org/10.1145/201310.201319","url":null,"abstract":"A genetic algorithm (GA) is a robust problem-solving method based on natural selection. Hardware's speed advantage and its ability to parallelize offer great rewards to genetic algorithms. Speedups of 1-3 orders of magnitude have been observed when frequently used software routines were implemented in hardware by way of reprogrammable field-programmable gate arrays (FPGAs). Reprogrammability is essential in a general-purpose GA engine because certain GA modules require changeability (e.g. the function to be optimized by the GA). Thus a hardware-based GA is both feasible and desirable. A fully functional hardware-based genetic algorithm (the HGA) is presented here as a proof-of-concept system. It was designed using VHDL to allow for easy scalability. It is designed to act as a coprocessor with the CPU of a PC. The user programs the FPGAs which implement the function to be optimized. Other GA parameters may also be specified by the user. Simulation results and performance analyses of the HGA are presented. A prototype HGA is described and compared to a similar GA implemented in software. In the simple tests, the prototype took about 6% as many clock cycles to run as the software-based GA. Further suggested improvements could realistically make the HGA 2-3 orders of magnitude faster than the software-based GA.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125530117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 188