TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation

Abstract

TIERS is a new pipelined routing and scheduling algorithm implemented in a completeVirtualWire TM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.