Third International ACM Symposium on Field-Programmable Gate Arrays最新文献_第2页

Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs 回顾基于查找表的fpga逻辑单元级联电路

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201325

N. Woo

引用次数: 11

Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses 支持ram和总线的fpga信号处理结构化数据路径的合成

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201323

B. Haroun, B. Sajjadi

引用次数: 0

PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs PathFinder:基于协商的fpga性能驱动路由器

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201328

L. McMurchie, C. Ebeling

{"title":"PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs","authors":"L. McMurchie, C. Ebeling","doi":"10.1145/201310.201328","DOIUrl":"https://doi.org/10.1145/201310.201328","url":null,"abstract":"Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133068987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 662

Architecture of Centralized Field-Configurable Memory 集中式字段可配置存储器的体系结构

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201326

S. Wilton, Jonathan Rose, Z. Vranesic

引用次数: 44

Design of FPGAs with Area I/O for Field Programmable MCM 现场可编程MCM的区域I/O fpga设计

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201313

V. Maheshwari, J. Darnauer, J. Ramirez, W. Dai

引用次数: 22

Logic Partition Orderings for Multi-FPGA Systems 多fpga系统的逻辑分区排序

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201315

S. Hauck, G. Borriello

引用次数: 32

Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays 非定制分段通道现场可编程门阵列的测试

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201330

Tong Liu, Wei-Kang Huang, F. Lombardi

{"title":"Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays","authors":"Tong Liu, Wei-Kang Huang, F. Lombardi","doi":"10.1145/201310.201330","DOIUrl":"https://doi.org/10.1145/201310.201330","url":null,"abstract":"This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original FPGA configuration of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]. The proposed approach requires 8+2n_f vectors for testing the uncommitted FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale], where nf is the number of flip-flops (equal to the number of sequential modules for the FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]) in a row of the FPGA.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116800372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

An SBus Monitor Board SBus监控板

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201335

H. A. Xie, K. Forward, K. M. Adams, D. Leask

{"title":"An SBus Monitor Board","authors":"H. A. Xie, K. Forward, K. M. Adams, D. Leask","doi":"10.1145/201310.201335","DOIUrl":"https://doi.org/10.1145/201310.201335","url":null,"abstract":"During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin bus connector and hence it is not practical to catch all the bus data required to ensure that such signals are in accordance with the bus specification. Hence a given connector specific bus monitor board is a necessary instrument to attach to the system motherboard in order to monitor all bus activities. A connector specific bus monitor board provides an efficient resource with which to study the internal philosophy of system software, the software implementation process for different communication layers, and to provide debugging for hardware developers. The bus monitor board described here is designed to attach to a SUN SBus and is similar to the Transformable Computer, which appeared recently, in that its architecture is reconfigurable via the use of a Field Programmable Gate Array (FPGA). It can be programmed to customise it to various users' specific needs. It differs from the Transformable Computer in that although it can be programmed to function as a coprocessor its primary function is dedicated SBus Monitoring. It is less costly than a Transformable Computer. In this article we describe the prototype of an SBus monitor's architecture and functions, and present the experimental results obtained from a Sun SPARC work station and an Aurora SBox Expansion Chassis, which demonstrate its ability to capture and display data communication and bus activity. Since this prototype board is programmable, it has the potential to provide many special purpose SBus monitors, but also function as a programmable coprocessor.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129271679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On Designing ULM-Based FPGA Logic Modules 基于ulm的FPGA逻辑模块设计

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201311

Shashidhar Thakur, D. F. Wong

{"title":"On Designing ULM-Based FPGA Logic Modules","authors":"Shashidhar Thakur, D. F. Wong","doi":"10.1145/201310.201311","DOIUrl":"https://doi.org/10.1145/201310.201311","url":null,"abstract":"In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrate the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Spectral-Based Multi-Way FPGA Partitioning 基于频谱的FPGA多路分区

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI: 10.1145/201310.201331

P. K. Chan, M. Schlag, Jason Y. Zien

引用次数: 38