基于ulm的FPGA逻辑模块设计

Shashidhar Thakur, D. F. Wong
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引用次数: 31

摘要

本文在对通用逻辑模块(ULM)设计经典工作进行扩展的基础上,提出了一种FPGA逻辑模块的设计方法。具体地说,我们给出了一种技术来设计一类逻辑模块,这些模块专门用于在输入的互补和置换、输入的桥接和0/1赋值下的大量函数。因此,可以使用单个逻辑模块实现许多功能。我们工作的意义在于我们能够生成大量这样的逻辑模块。可以根据设计标准从这个集合中进行选择。我们通过生成一组471个8输入函数来演示该技术,这些函数比Actel的fpga采用的8输入单元具有更高的覆盖率。我们的函数可以专门化到Actel函数数量的23倍。我们还表明,通过仔细优化这些函数,可以获得它们的多级实现,其延迟在Actel模块延迟的10%以内。我们证明了这些模块在映射基准电路中的有效性。我们观察到,在这些电路上使用我们的逻辑模块而不是Actel的逻辑模块,面积减少了16%,延迟减少了21%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
On Designing ULM-Based FPGA Logic Modules
In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrate the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.
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