层:拓扑无关的流水线路由和调度的VirtualWire™编译

Third International ACM Symposium on Field-Programmable Gate Arrays Pub Date : 1995-02-15 DOI:10.1145/201310.201314

C. Selvidge, A. Agarwal, M. Dahl, J. Babb

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引用次数: 39

摘要

TIERS是在一个完整的virtualwire TM编译和合成系统中实现的一种新的流水线路由和调度算法。对各层进行了描述，并与之前的工作进行了分析和定量的比较。与之前的工作相比，分层将系统速度提高了2.5倍。给出了基于Altera和Xilinx的FPGA系统的层路由结果。

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TIERS: Topology IndependEnt Pipelined Routing and Scheduling for VirtualWire™ Compilation

TIERS is a new pipelined routing and scheduling algorithm implemented in a completeVirtualWire TM compilation and synthesis system. TIERS is described and compared to prior work both analytically and quantitatively. TIERS improves system speed by as much as a factor of 2.5 over prior work. TIERS routing results for both Altera and Xilinx based FPGA systems are provided.

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Third International ACM Symposium on Field-Programmable Gate Arrays

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