2014 25nd IEEE International Symposium on Rapid System Prototyping最新文献

Prototyping and performance evaluation of a dynamically adaptable block device driver for PCIe-based SSDs 基于pcie的固态硬盘动态适应块设备驱动程序的原型设计和性能评估

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966692

E. Bougioukou, Athina Ntalla, Aspa Palli, M. Varsamou, T. Antonakopoulos

引用次数: 6

Product line development for modular FPGA-based embedded systems 基于模块化fpga的嵌入式系统产品线开发

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966686

Till Fischer, C. Köllner, Manuel Hardle, K. Müller-Glaser

{"title":"Product line development for modular FPGA-based embedded systems","authors":"Till Fischer, C. Köllner, Manuel Hardle, K. Müller-Glaser","doi":"10.1109/RSP.2014.6966686","DOIUrl":"https://doi.org/10.1109/RSP.2014.6966686","url":null,"abstract":"Managing different variants and configurations of complex embedded systems consisting of multiple exchangeable hardware modules is a difficult task. This is in particular true when selecting a certain variant and configuration affects several aspects of development, deployment and operation. In this paper, we describe our approach for product line development of a highly flexible, modular embedded system, which can be assembled in many different ways. Each composition can be perceived as a prototype, because it requires a specific FPGA firmware, and offers different parameters changeable at runtime. A key component of our solution is a model-based description of possible variations. It enables automatic generation of source code as well as configuration files. Through this it is possible to provide new variants and configurations very fast and the response time to customer requests is improved. We outline how the model can be well-integrated with technologies and tools used for development, deployment and operation of the overall system. This involves run-time parametrization of the system and configuration of secondary tools using standard office documents, but the focus lies on the link between model and FPGA implementation (VHDL). We propose a powerful but still easy to understand template-based approach for this purpose.","PeriodicalId":394637,"journal":{"name":"2014 25nd IEEE International Symposium on Rapid System Prototyping","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117218770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Device driver generation targeting multiple operating systems using a model-driven methodology 使用模型驱动的方法生成针对多个操作系统的设备驱动程序

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966689

Hui Chen, G. Godet-Bar, F. Rousseau, F. Pétrot

引用次数: 8

Architecture models refinement for fine grain timing analysis of embedded systems 嵌入式系统细粒度时序分析的体系结构模型改进

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966691

Etienne Borde, Smail Rahmoun, Fabien Cadoret, L. Pautet, Frank Singhoff, P. Dissaux

引用次数: 17

System-on-chip processor using different FPGA architectures in the VTR CAD flow 片上系统处理器采用不同的FPGA架构在VTR CAD流程中实现

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966895

Jingjing Li, K. Nasartschuk, K. Kent

引用次数: 3

Wireless network-on-chip: a new era in multi-core chip design 无线片上网络:多核芯片设计的新时代

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966893

Sujay Deb, H. Mondal

引用次数: 9

FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC) 网络物理片上系统(CPSoC)的FPGA仿真与原型设计

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966902

S. Sarma, N. Dutt

{"title":"FPGA emulation and prototyping of a cyberphysical-system-on-chip (CPSoC)","authors":"S. Sarma, N. Dutt","doi":"10.1109/RSP.2014.6966902","DOIUrl":"https://doi.org/10.1109/RSP.2014.6966902","url":null,"abstract":"Cyber-Physical Systems-on-Chip (CPSoC) are a new class of sensor- and actuator-rich multiprocessor system-on-chips (MPSoCs) whose operations are monitored, coordinated, and controlled using a computing-communication-control (C3) centric core with additional on-chip and cross-layer sensing and actuation capabilities that enable self-awareness within the observe-decide-act (ODA) paradigm. In order to build, evaluate, and illustrate the effectiveness of various features of this new MPSoC paradigm in a fast and cost effective way, a rapid prototyping and emulation platform along with the tool chains is absolutely necessary. In this paper, we present a design library and an FPGA emulation and prototyping platform to build and investigate self-aware adaptive computing using CPSoC paradigm. Our example implementation of CPSoC prototyping using Xilinx FPGAs includes ring-oscillator (RO) based multipurpose sensors integrated with a sensor network-on-chip (sNoC) which in turn is interfaced either to a bus based shared memory architecture or to a communication and computation network-on- chip (cNoC) distributed fabric supporting several actuation mechanism in the software and hardware stack. We also briefly discuss few applications of the CPSoC design library and the platform.","PeriodicalId":394637,"journal":{"name":"2014 25nd IEEE International Symposium on Rapid System Prototyping","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126041923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs 周期约束下3d - mpsoc峰值温度最小化的热感知任务调度

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966900

Vivek Chaturvedi, A. Singh, Wei Zhang, T. Srikanthan

引用次数: 15

DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems DRAC:用于多核嵌入式系统混合原型的动态可重构活动L1缓存模型

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966897

Ali Barzegar, Ehsan Saboori, S. Abdi

引用次数: 2

SF3P: a framework to explore and prototype hierarchical compositions of real-time schedulers SF3P:一个用于探索和原型化实时调度器分层组合的框架

2014 25nd IEEE International Symposium on Rapid System Prototyping Pub Date : 2014-12-01 DOI: 10.1109/RSP.2014.6966685

Andres Gomez, Lars Schor, Pratyush Kumar, L. Thiele

{"title":"SF3P: a framework to explore and prototype hierarchical compositions of real-time schedulers","authors":"Andres Gomez, Lars Schor, Pratyush Kumar, L. Thiele","doi":"10.1109/RSP.2014.6966685","DOIUrl":"https://doi.org/10.1109/RSP.2014.6966685","url":null,"abstract":"The trend to integrate multiple functionalities on the same (off-the-shelf) hardware has made the selection of the right scheduling algorithm and configuration difficult. This selection requires the designer to validate any scheduling decision already during early design steps on the target architecture, e.g., by using a reconfigurable scheduling framework running in the user-space. In this paper, we first identify the requirements that such a scheduling framework must fulfill. Then, we propose SF3P: an open-source framework that meets these requirements. To this end, we define an interface common to all scheduling algorithms and separate the scheduling algorithm from its low-level implementation. With these features, SF3P can not only prototype a scheduler at high level of abstraction, but also execute the implemented task-set on specific hardware. Furthermore, SF3P can hierarchically compose scheduling algorithms, useful in the mixed criticality domain, and could also be used to explore different scheduling policies in the system optimization phase. We demonstrate these features by implementing SF3P on top of a POSIX-compliant operating system on two different platforms: Raspberry Pi and an Intel Core i7 desktop system.","PeriodicalId":394637,"journal":{"name":"2014 25nd IEEE International Symposium on Rapid System Prototyping","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122956124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13