2021 International Conference on System, Computation, Automation and Networking (ICSCAN)最新文献

A Comparative Study to analyze crime threats using data mining and machine learning approach 使用数据挖掘和机器学习方法分析犯罪威胁的比较研究

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526489

Puninder Kaur, G. Rani, Taruna Sharma, Avinash Sharma

引用次数: 1

Digital Implementation of Radar Receiver and Signal Processing Algorithms 雷达接收机的数字化实现与信号处理算法

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526463

Suraj Bhan Rathor, Shashikiran Dayalan, A. B. Bazil Raj

{"title":"Digital Implementation of Radar Receiver and Signal Processing Algorithms","authors":"Suraj Bhan Rathor, Shashikiran Dayalan, A. B. Bazil Raj","doi":"10.1109/ICSCAN53069.2021.9526463","DOIUrl":"https://doi.org/10.1109/ICSCAN53069.2021.9526463","url":null,"abstract":"This paper details the implementation of Radar Receiver and Signal Processing algorithms on a Kintex-7 FPGA based board and the results obtained. Radar receiver receives and enhances the target echoes with noise and clutter. The major blocks of a Digital Radar Receiver are Digital Down Converter (DDC) which is used to convert an RF or IF signal down to baseband by sampling the signal at suitably high sample rates and then using purely digital techniques to obtain baseband data. Radar Signal Processing algorithms extracts targets from the background interference (noise + jammer) and passes the information to Data Processor for tracking and further action. The major blocks of Radar Signal Processing are Pulse Compression, MTI, Doppler Filtering, CFAR and target angle estimation. The conventional DDC (Single Stage FIR filter) was implemented on a Kintex-7 FPGA – XC7K325TFBG900-1 device using Vivado 2014.4 tool and the Radar Signal Processing chain was implemented using Code Blocks IDE Software using C/C++ language. The implementation was targeted to reduce hardware complexity, enhance speed and reduce power dissipation. The results are analysed using Vivado Simulator and MATLAB tools.","PeriodicalId":393569,"journal":{"name":"2021 International Conference on System, Computation, Automation and Networking (ICSCAN)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127345009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Dynamic Quick Sort Algorithmic Approach For Opitimizing Power And Spatial Mapping In SOC SOC中功率与空间映射优化的动态快速排序算法

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526441

K. Sangeetha, K. Anuratha, R. Devi, S. S. Shamini

{"title":"Dynamic Quick Sort Algorithmic Approach For Opitimizing Power And Spatial Mapping In SOC","authors":"K. Sangeetha, K. Anuratha, R. Devi, S. S. Shamini","doi":"10.1109/ICSCAN53069.2021.9526441","DOIUrl":"https://doi.org/10.1109/ICSCAN53069.2021.9526441","url":null,"abstract":"The growth of the microelectronics industry has increased the demand for portable devices with three key factors such as speed, area utilized and low power consumption. For devices with high performance applications, power reduction is a major concern. The Coarse Grained Reconfigurable Architectures (CGRAs) are used in embedded systems and Internet of Things with simultaneous high programmability and high power efficiency. The CGRA’s compiler has to efficiently map the looping operations to its limited resources. One of the major problems faced is efficient mapping of applications to CGRA. Existing methods deal with the static mapping algorithms. In our proposed method we use Dynamic quick sort mapping algorithm which allows power optimization along with dynamic mapping technique. All the modules needed for the system are developed and integrated on a single chip thereby it reduce the area utilized. Thus it is called as System On Chip (SOC). Due to more flexibility in the systems, runtimes become lengthier and delay is increased. In our system the delay is reduced to 7 to 8 nanoseconds, thus effective use of CGRA is obtained along with the low power consumption and area reduction.","PeriodicalId":393569,"journal":{"name":"2021 International Conference on System, Computation, Automation and Networking (ICSCAN)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124801426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An Effective Implementation of Vehicle Document Verification Using Genetic Algorithm 基于遗传算法的车辆证件验证的有效实现

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526394

G. Premalatha, S. Abinaya

{"title":"An Effective Implementation of Vehicle Document Verification Using Genetic Algorithm","authors":"G. Premalatha, S. Abinaya","doi":"10.1109/ICSCAN53069.2021.9526394","DOIUrl":"https://doi.org/10.1109/ICSCAN53069.2021.9526394","url":null,"abstract":"Throughout the world, according to the act of motor vehicle , each citizen should carry the original records like (Insurance, License, and Registration certificates book). While driving citizens need to carry all the original documents , many of them fail to carry their documents and facing difficulties . To defeat this issue , the proposed system created an individual barcode and their details are stored in the RTO database which consists of personal details , license , registration books (RC), and insurance . By using MATLAB, the barcode scanner will be done and it will decode the barcode to find the documents in the RTO database , suppose any of the documents are missing in the RTO database or insurance is not up-to-date than the person who maintains the RTO database will generate a fine amount for the consenting person. After paying that he/she needs to update the insurance in the RTO database . Suppose the barcode is missing in the vehicle they need to pay the fine and if they did not pay the fine amount then their vehicle should be taken under the control of the RTO . This database is fully monitored by the RTO . Thi sproject helps to reduce the work of the police officer and help to follow the rules acco rding to the Motor Vehicle Act.","PeriodicalId":393569,"journal":{"name":"2021 International Conference on System, Computation, Automation and Networking (ICSCAN)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126059084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of Digital Architecture for Custom Implementation of Cordic Algorithm Cordic算法自定义实现的数字架构设计

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526417

Putchala Santosh Kumar, Prajapati Vatsalkumar, Snehasis Dolui, N. Khan, A. B. Bazil Raj

{"title":"Design of Digital Architecture for Custom Implementation of Cordic Algorithm","authors":"Putchala Santosh Kumar, Prajapati Vatsalkumar, Snehasis Dolui, N. Khan, A. B. Bazil Raj","doi":"10.1109/ICSCAN53069.2021.9526417","DOIUrl":"https://doi.org/10.1109/ICSCAN53069.2021.9526417","url":null,"abstract":"An efficient way of obtaining trigonometric, hyperbolic, linear, and logarithmic is provided by the CORDIC algorithm. In this algorithm bit shifting operation replaces multiplication and iterative addition will result in accurate values of such trigonometric functions. Not only it is saving the area but also improves the throughput. This algorithm has become a widely researched area in the field of vector rotated DSP applications. This paper explores the basic CORDIC algorithm and implements it on FPGA using VHDL coding. Uniqueness in the proposed CORDIC algorithm is that 4-bit input will cover all the values of angle in four quadrants having a resolution of 22.5°. Using recent technology, we can have to utilize more hardware in order to achieve speed constraints. A serial iterative CORDIC uses less hardware with more latency so, here to have high throughput parallel iterative hardware is used. But The bit-parallel variable shift shifters require high fan-in. As FPGA provides both flexibility as well as speed it is much better choice for implementing CORDIC algorithm. The proposed CORDIC algorithm is simulated on Vivado 2019.2 and implemented on the Xilinx Spartan 3E board. The simulation results which are shown below verify the authenticity and validity of the designed CORDIC algorithm.","PeriodicalId":393569,"journal":{"name":"2021 International Conference on System, Computation, Automation and Networking (ICSCAN)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126139859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Development of Health Monitoring Vest using Velostat 利用Velostat研制健康监测背心

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526519

M. Kanimozhi, I. Yamuna, B. Srimathi, SENTHIL KUMARAN RAJENDRAN

引用次数: 0

Parkinson Disease Detection Based On Speech Using Various Machine Learning Models and Deep Learning Models 基于语音的帕金森病检测，使用各种机器学习模型和深度学习模型

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526372

V. P, Tharani Priya B, Anu Rithiga B, Bhuvaneaswari R

{"title":"Parkinson Disease Detection Based On Speech Using Various Machine Learning Models and Deep Learning Models","authors":"V. P, Tharani Priya B, Anu Rithiga B, Bhuvaneaswari R","doi":"10.1109/ICSCAN53069.2021.9526372","DOIUrl":"https://doi.org/10.1109/ICSCAN53069.2021.9526372","url":null,"abstract":"Parkinson disease is a neurodegenerative disorder. Parkinson disease is the nervous disorder that affects the movements. Early symptoms of parkinson disease are speech impairment, tremor, bradykinesia, writing changes and so on. Parkinson disease cannot be cured but earlier detection and medication can improve the symptoms. So the early detection of parkinson disease is very important. As the dataset is unbalanced, model can become biased to one class.So balancing of dataset is very important. Dataset can be balanced using oversampling technique. So we propose the prediction of parkinson disease based on speech by using various machine learning with and without oversampling on various dataset and the accuracy and other performance metrics of various models are compared. So the model with better performance metrics is identified. Extreme gradient boosting algorithm acquired the highest accuracy of 96%.Further, the Extreme gradient boosting algorithm is improved by using the various optimization techniques that tunes the hyper parameters of the models. The accuracy obtained after optimization is about 97%.","PeriodicalId":393569,"journal":{"name":"2021 International Conference on System, Computation, Automation and Networking (ICSCAN)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-07-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122456215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

PV Combined ZSI-DVR with Fuzzy Logic Controller for Power Quality Improvement 光伏组合ZSI-DVR与模糊控制器改善电能质量

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526539

A. Jeraldineviji, R. Priya, B. Pushpa

引用次数: 1

Reduced Radar Cross-Section Target Imaging System 简化雷达横截面目标成像系统

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526517

Mvs Kameshwara Rao, A. B. Bazil Raj

引用次数: 0

Optimization of Resource Allocation in Mobile Edge Computing using Bio-Inspired Algorithm 基于仿生算法的移动边缘计算资源分配优化

2021 International Conference on System, Computation, Automation and Networking (ICSCAN) Pub Date : 2021-07-30 DOI: 10.1109/ICSCAN53069.2021.9526479

C. Anuradha, M. Ponnavaikko

引用次数: 1