Digital Implementation of Radar Receiver and Signal Processing Algorithms

This paper details the implementation of Radar Receiver and Signal Processing algorithms on a Kintex-7 FPGA based board and the results obtained. Radar receiver receives and enhances the target echoes with noise and clutter. The major blocks of a Digital Radar Receiver are Digital Down Converter (DDC) which is used to convert an RF or IF signal down to baseband by sampling the signal at suitably high sample rates and then using purely digital techniques to obtain baseband data. Radar Signal Processing algorithms extracts targets from the background interference (noise + jammer) and passes the information to Data Processor for tracking and further action. The major blocks of Radar Signal Processing are Pulse Compression, MTI, Doppler Filtering, CFAR and target angle estimation. The conventional DDC (Single Stage FIR filter) was implemented on a Kintex-7 FPGA – XC7K325TFBG900-1 device using Vivado 2014.4 tool and the Radar Signal Processing chain was implemented using Code Blocks IDE Software using C/C++ language. The implementation was targeted to reduce hardware complexity, enhance speed and reduce power dissipation. The results are analysed using Vivado Simulator and MATLAB tools.