Dynamic Quick Sort Algorithmic Approach For Opitimizing Power And Spatial Mapping In SOC

The growth of the microelectronics industry has increased the demand for portable devices with three key factors such as speed, area utilized and low power consumption. For devices with high performance applications, power reduction is a major concern. The Coarse Grained Reconfigurable Architectures (CGRAs) are used in embedded systems and Internet of Things with simultaneous high programmability and high power efficiency. The CGRA’s compiler has to efficiently map the looping operations to its limited resources. One of the major problems faced is efficient mapping of applications to CGRA. Existing methods deal with the static mapping algorithms. In our proposed method we use Dynamic quick sort mapping algorithm which allows power optimization along with dynamic mapping technique. All the modules needed for the system are developed and integrated on a single chip thereby it reduce the area utilized. Thus it is called as System On Chip (SOC). Due to more flexibility in the systems, runtimes become lengthier and delay is increased. In our system the delay is reduced to 7 to 8 nanoseconds, thus effective use of CGRA is obtained along with the low power consumption and area reduction.