Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, M. Glesner, F. Moraes, J. Nurmi
{"title":"Characterising embedded applications using a UML profile","authors":"Sanna Määttä, L. Indrusiak, Luciano Ost, Leandro Möller, M. Glesner, F. Moraes, J. Nurmi","doi":"10.1109/SOCC.2009.5335654","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335654","url":null,"abstract":"Application designers need to start the application design process before the final platform is available. Therefore, the designers need to have an abstract model of the platform at the early stages of the design process in order to validate the application functionality and evaluate its performance. Furthermore, platform designers need an application model to evaluate whether the computation and communication capacity of the platform is sufficient for the application. This paper identifies a minimalistic set of modelling constructs that can extensively characterise an application, which can be validated over a multicore Network-on-Chip (NoC) platform. The identified set of constructs is organized as a Unified Modeling Language (UML) profile in order to facilitate its use within UML-based design flows and tools. We present a practical application using the profile's constructs to model and constrain several subsystems of an autonomous vehicle control. Using the profile, we can cover sufficient aspects of the computation and communication requirements of the application, so that we can perform an extensive comparative analysis of alternative platform configurations very early in the design flow.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114987476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Samuel Rodrigo, Carles Hernández, J. Flich, F. Silla, J. Duato, S. Medardoni, D. Bertozzi, A. Mejia, Donglai Dai
{"title":"Yield-oriented evaluation methodology of network-on-chip routing implementations","authors":"Samuel Rodrigo, Carles Hernández, J. Flich, F. Silla, J. Duato, S. Medardoni, D. Bertozzi, A. Mejia, Donglai Dai","doi":"10.1109/SOCC.2009.5335667","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335667","url":null,"abstract":"Network-on-Chip technology is gaining wide popularity for the interconnection of an increasing number of processor cores on the same silicon die. However, growing process variations cause interconnect malfunction or prevent the network from working at the intended frequency, directly impacting yield and manufacturing cost. Topology agnostic routing algorithms have the potential to tolerate process variations without degrading performance. We propose a three step methodology for evaluating routing algorithms in their ability to deal with variability. Using yield enhancement and operation speed preservation as the criteria, we demonstrate how this methodology can be used to select the best design choice among several plausible combinations of routing algorithms and implementations. Also, we show how an efficient table-less routing implementation can be used to minimise the impact of variability on manufacturing and operating frequency.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"83 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128674375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Building asynchronous routers with independent sub-channels","authors":"Wei Song, D. Edwards","doi":"10.1109/SOCC.2009.5335680","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335680","url":null,"abstract":"Network-on-chip (NoC) has been used as the new on-chip communication paradigm. Asynchronous NoCs are power efficient and robust to process variation but they are slow. One reason for the low speed is the way that asynchronous routers use to build wide channels. To meet the bandwidth requirement, current routers broaden their channels by synchronizing multiple sub-channels. The C-element and buffer trees introduced by the synchronization increase the cycle period. A new router is proposed to use multiple independent sub-channels to transmit data. Since the synchronization is removed, the cycle period of all sub-channels are reduced speeding up the network. Two routers, one using multiple independent sub-channels and one using the synchronized wide channel, are implemented at the layout level. The simulation results show that the new router using multiple independent sub-channels reduces the router latency and the cycle period.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134100945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A checkpoint/restore framework for systemc-based virtual platforms","authors":"S. Kraemer, R. Leupers, D. Petras, Thomas Philipp","doi":"10.1109/SOCC.2009.5335656","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335656","url":null,"abstract":"The ability to restore a Virtual Platform from a previously saved simulation state can considerably shorten the typical edit-compile-debug cycle for software developers and therefore enhance productivity. This paper presents a Checkpoint/Restore solution specifically tailored towards the needs of SystemC-based Virtual Platforms. Apart from restoring the simulation process from a checkpoint image, it also takes care of re-attaching debuggers and interactive GUIs to the restored Virtual Platform. The checkpointing is handled automatically for most of the SystemC modules, only the usage of host OS resources requires user provision. Two concrete code examples demonstrate that the required changes to an existing Virtual Platform are a simple developer task consisting of minor source code modifications. A case study based on the SHAPES Virtual Platform is conducted to investigate the applicability of the proposed framework in a realistic system environment.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129340883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Multi-compartment: A new architecture for secure co-hosting on SoC","authors":"J. Porquet, Christian Schwarz, A. Greiner","doi":"10.1109/SOCC.2009.5335664","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335664","url":null,"abstract":"Multi-compartment is a flexible, lightweight architecture for embedded systems that allows multiple protection domains (compartments) to securely share processing, memory and other system resources. Compartments run in physical address space and enjoy direct access to security-critical initiator devices, such as DMA devices, while remaining protected from one another.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121833298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhenyu Tu, Meng Yu, D. Iancu, M. Moudgill, C. Glossner
{"title":"On the performance of 3GPP LTE baseband using SB3500","authors":"Zhenyu Tu, Meng Yu, D. Iancu, M. Moudgill, C. Glossner","doi":"10.1109/SOCC.2009.5335659","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335659","url":null,"abstract":"In this paper, we present the system and computational performance of 3GPP LTE baseband processing implemented on the Sandbridge SB3500 processor. Maximum Ratio Combiner (MRC) and Linear Minimum Mean Square (LMMSE) are adopted to be the baseline receiver algorithm for various downlink transmission modes. The system performance evaluation, through end-to-end system simulations, shows that the conformance test requirements published by the 3GPP group are met with a design margin ranging from 0.8 to 2 dB. The computational complexity of our LTE category 2 implementation is such that the entire baseband processing executes in one SB3500 processor.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122636624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic workload peak detection for slack management","authors":"Aleksandar Milutinovic, K. Goossens, G. Smit","doi":"10.1109/SOCC.2009.5335679","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335679","url":null,"abstract":"In this paper an analytical study on dynamism and possibilities on slack exploitation by dynamic power management is presented. We introduce a specific workload decomposition method for work required for (streaming) application processing data tokens (e.g. video frames) with work behaviour patterns as a mix of periodic and aperiodic patterns. It offers efficient and computationally light method for speculation on considerable work variations and its exploitation in energy saving techniques. It is used by a dynamic power management policy which has low overhead and reduces both requirements for buffering space, and deadline misses (increase QoS). We evaluate our policy in experiments on MPEG4 decoding of several different input sequences and present results.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131022551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Ghavami, H. Zarandi, Arezoo Salarpour, H. Pedram
{"title":"Diagnosis of faults in template-based asynchronous circuits","authors":"B. Ghavami, H. Zarandi, Arezoo Salarpour, H. Pedram","doi":"10.1109/SOCC.2009.5335682","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335682","url":null,"abstract":"This paper presents an intrinsically verifiable library of quasi delay insensitive asynchronous templates providing an efficient debugging platform for large asynchronous circuits. We proposed using state transition graph to determining necessary properties which must be checked. For every template of a pre-charged full buffer library, we defined PSL properties which are used as monitors verifying correctness of necessary handshaking protocols between templates under simulation. Experimental results show that with a 8% increase in simulation time, all faults in handshaking protocols can be detected.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124283645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Skeie, F. Sem-Jacobsen, Samuel Rodrigo, J. Flich, D. Bertozzi, S. Medardoni
{"title":"Flexible DOR routing for virtualization of multicore chips","authors":"T. Skeie, F. Sem-Jacobsen, Samuel Rodrigo, J. Flich, D. Bertozzi, S. Medardoni","doi":"10.1109/SOCC.2009.5335673","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335673","url":null,"abstract":"The expected increase in number of cores on a single chip leads to the necessity of high-performance on chip interconnects (NoC). Furthermore, in order to fully utilize the abundance of cores, the chip is expected to support a number of applications running on the chip simultaneously. It is therefore necessary to partition the chip to support numerous applications without any risk of interference between them. The success of this depends on the flexibility of the underlying routing algorithm. This paper presents a flexible routing algorithm based on dimension ordered routing, which supports a large variety of irregular (2-D and 3-D) mesh topologies. The algorithm provides high efficiency at very low additional complexity, as is confirmed by experimental results.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128849328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A DSP architecture optimized for wireless baseband","authors":"C. Rowen, P. Nuth, S. Fiske","doi":"10.1109/SOCC.2009.5335658","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335658","url":null,"abstract":"The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations such as LTE. The Tensilica ConnX Baseband Engine processor core implements a 3-issue VLIW, 8-way SIMD architecture. It can perform 16 multiply-add operations per cycle, and executes a full radix-4 FFT butterfly or 4 complex FIR filter taps per cycle. It directly implements vector division and reciprocal square root operations. At 400MHz, it provides almost 13GB per second of memory bandwidth. The rich programming environment, including vectorization of scalar C applications, allows easy deployment into cellular base-station, femto-cell and other software-agile radio applications, and into multi-standard broadcast receivers.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"2010 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121009943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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