2009 International Symposium on System-on-Chip最新文献_第4页

Performance analysis of LTE protocol processing on an ARM based mobile platform 基于ARM的移动平台上LTE协议处理性能分析

2009 International Symposium on System-on-Chip Pub Date : 2009-10-05 DOI: 10.1109/SOCC.2009.5335678

David Szczesny, Anas Showk, S. Hessel, A. Bilgic, Uwe Hildebrand, V. Frascolla

{"title":"Performance analysis of LTE protocol processing on an ARM based mobile platform","authors":"David Szczesny, Anas Showk, S. Hessel, A. Bilgic, Uwe Hildebrand, V. Frascolla","doi":"10.1109/SOCC.2009.5335678","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335678","url":null,"abstract":"In this paper we present detailed profiling results and identify the time critical algorithms of the Long Term Evolution (LTE) layer 2 (L2) protocol processing on an ARM based mobile hardware platform. Furthermore, we investigate the applicability of a single ARM processor combined with a traditional hardware acceleration concept for the significantly increased computational demands in LTE and future mobile devices. A virtual prototyping approach is adopted in order to simulate a state-of-the-art mobile phone platform which is based on an ARM1176 core. Moreover a physical layer and base station emulator is implemented that allows for protocol investigations on transport block level at different transmission conditions. By simulating LTE data rates of 100 Mbit/s and beyond, we measure the execution times in a protocol stack model which is compliant to 3GPP Rel.8 specifications and comprises the most processing intensive downlink (DL) part of the LTE L2 data plane. We show that the computing power of a single embedded processor at reasonable clock frequencies is not enough to cope with the L2 requirements of next generation mobile devices. Thereby, Robust Header Compression (ROHC) processing is identified as the major time critical software algorithm, demanding half of the entire L2 DL execution time. Finally, we illustrate that a conventional hardware acceleration approach for the encryption algorithms fails to offer the performance required by LTE and future mobile phones.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122757512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 44

Automatic generation of memory interfaces

2009 International Symposium on System-on-Chip Pub Date : 2009-10-05 DOI: 10.1109/SOCC.2009.5335674

D. Kammler, Bastian Bauwens, E. M. Witte, G. Ascheid, R. Leupers, H. Meyr, A. Chattopadhyay

引用次数: 1

Performance analysis of multi-channel memories in mobile devices 移动设备中多通道存储器性能分析

2009 International Symposium on System-on-Chip Pub Date : 2009-10-05 DOI: 10.1109/SOCC.2009.5335661

Jari Nikara, E. Aho, Petri A. Tuominen, Kimmo Kuusilinna

引用次数: 6

Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs 基于noc的mpsoc中静态和动态任务映射算法的评估

2009 International Symposium on System-on-Chip Pub Date : 2009-10-05 DOI: 10.1109/SOCC.2009.5335672

Ewerson Carvalho, C. Marcon, Ney Laert Vilar Calazans, F. Moraes

{"title":"Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs","authors":"Ewerson Carvalho, C. Marcon, Ney Laert Vilar Calazans, F. Moraes","doi":"10.1109/SOCC.2009.5335672","DOIUrl":"https://doi.org/10.1109/SOCC.2009.5335672","url":null,"abstract":"Task mapping is an important issue in MPSoC design. Most recent mapping algorithms perform them at design time, an approach known as static mapping. Nonetheless, applications running in MPSoCs may execute a varying number of simultaneous tasks. In some cases, applications may be defined only after system design, enforcing a scenario that requires the use of dynamic task mapping. Static mappings have as main advantage the global view of the system, while dynamic mappings normally provide a local view, which considers only the neighborhood of the mapping task. This work aims to evaluate the pros and cons of static and dynamic mapping solutions. Due to the global system view, it is expected that static mapping algorithms achieve superior performance (w.r.t. latency, congestion, energy consumption). As dynamic scenarios are a trend in present MPSoC designs, the cost of dynamic mapping algorithms must be known, and directions to improve the quality of such algorithms should be provided without increasing execution time. This quantitative comparison between static and dynamic mapping algorithms is the main contribution of this work.","PeriodicalId":389625,"journal":{"name":"2009 International Symposium on System-on-Chip","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120988089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 41

RTL-to-layout implementation of an embedded coarse grained architecture for dynamically reconfigurable computing in systems-on-chip 用于片上系统中动态可重构计算的嵌入式粗粒度架构的RTL-to-layout实现

2009 International Symposium on System-on-Chip Pub Date : 2009-10-05 DOI: 10.1109/SOCC.2009.5335665

F. Campi, Ralf König, M. Dreschmann, M. Neukirchner, Damien Picard, M. Jüttner, Eberhard Schüler, A. Deledda, D. Rossi, A. Pasini, M. Hübner, J. Becker, R. Guerrieri

引用次数: 14