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2009 IEEE International Symposium on Circuits and Systems最新文献

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Joint texture and depth map video coding based on the scalable extension of H.264/AVC 基于H.264/AVC可伸缩扩展的纹理和深度图联合视频编码
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118272
Siping Tao, Ying Chen, M. Hannuksela, Ye-Kui Wang, M. Gabbouj, Houqiang Li
{"title":"Joint texture and depth map video coding based on the scalable extension of H.264/AVC","authors":"Siping Tao, Ying Chen, M. Hannuksela, Ye-Kui Wang, M. Gabbouj, Houqiang Li","doi":"10.1109/ISCAS.2009.5118272","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118272","url":null,"abstract":"Depth-Image-Based Rendering (DIBR) is widely used for view synthesis in 3D video applications. Compared with traditional 2D video applications, both the texture video and its associated depth map are required for transmission in a communication system that supports DIBR. To efficiently utilize limited bandwidth, coding algorithms, e.g. the Advanced Video Coding (H.264/AVC) standard, can be adopted to compress the depth map using the 4:0:0 chroma sampling format. However, when the correlation between texture video and depth map is exploited, the compression efficiency may be improved compared with encoding them independently using H.264/AVC. A new encoder algorithm which employs Scalable Video Coding (SVC), the scalable extension of H.264/AVC, to compress the texture video and its associated depth map is proposed in this paper. Experimental results show that the proposed algorithm can provide up to 0.97 dB gain for the coded depth maps, compared with the simulcast scheme, wherein texture video and depth map are coded independently by H.264/AVC.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Temperature compensation in combination selection based mismatch calibration 基于错配校准的组合选择温度补偿
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118074
J. Marku, J. Poikonen, A. Paasio
{"title":"Temperature compensation in combination selection based mismatch calibration","authors":"J. Marku, J. Poikonen, A. Paasio","doi":"10.1109/ISCAS.2009.5118074","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118074","url":null,"abstract":"The temperature behaviour of a combination selection based mismatch calibration is discussed. The functionality of the calibration structure has already been presented. Clear benefits in implementation area and accuracy can be reached when using mismatch calibration based on combination selection of minimum-sized transistors. However, with the used high accuracy requirements, the effects of temperature must be taken into the account. Temperature compensation circuitry for combination selection based mismatch calibration is developed, designed and simulated. The new temperature compensated and mismatch calibrated current source achieves 99% accuracy in 4σ confidence over the temperature range of 30 degrees in centigrade. This range can still be extended by recalibrating the current source in intervals of 15 degrees in centigrade.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122160222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators 基于CAL规范和硬件/软件代码生成器的硬件/软件协同设计集成环境
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117876
Ghislain Roquier, Christophe Lucarz, M. Mattavelli, M. Wipliez, M. Raulet, J. Janneck, Ian D. Miller, D. Parlour
{"title":"An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators","authors":"Ghislain Roquier, Christophe Lucarz, M. Mattavelli, M. Wipliez, M. Raulet, J. Janneck, Ian D. Miller, D. Parlour","doi":"10.1109/ISCAS.2009.5117876","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117876","url":null,"abstract":"This demonstration presents an integrated environment that translates a CAL-based dataflow specification [1] into a heterogeneous implementation, composed by HDL and C codes. The demonstration focuses on the capability of the co-design environment to automatically build an executable heterogeneous system implementation running on a platform composed of a processor and a FPGA from the annotation of the CAL specification. The possibility of direct synthesis from a high level specification is a crucial issue for enabling efficient re-design cycles that include rapid prototyping and validation of performances of the final implementation. The design approach enabled by such integrated environment is particularly suited for development of complex processing systems such as video codecs. As a case study, the demonstration provides the analysis and validation of different software and hardware partitioning of a MPEG-4 Simple Profile decoder.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"48 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116842622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Low-complexity adaptive channel estimation for OFDM system in fast-fading channel 快速衰落信道下OFDM系统的低复杂度自适应信道估计
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117841
I-Wei Lai, Tsung-Han Yu, T. Chiueh
{"title":"Low-complexity adaptive channel estimation for OFDM system in fast-fading channel","authors":"I-Wei Lai, Tsung-Han Yu, T. Chiueh","doi":"10.1109/ISCAS.2009.5117841","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117841","url":null,"abstract":"This paper presents a low-complexity interpolation-based channel estimator suited for scattered-pilot OFDM systems in fast-fading channel. The proposed estimator consists of two interpolators: one RLS interpolator for estimating scattered subcarriers along the time direction and another raised-cosine (RC) interpolator for estimating data subcarriers along the frequency direction. A low-complexity architecture tailored for DVB-T/H is demonstrated as an exemplar. Simulation results show that the proposed channel estimator has comparable accuracy with almost order-of-magnitude lower complexity than conventional adaptive channel estimators.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117024195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Implementation and prototyping of a complex multi-project system-on-a-chip 一个复杂的多项目单片系统的实现和原型设计
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118264
Chun-Ming Huang, Chien‐Ming Wu, Chih-Chyau Yang, Wei-De Chien, Shih-Lun Chen, Chi-Shi Chen, J. Wang, C. Wey
{"title":"Implementation and prototyping of a complex multi-project system-on-a-chip","authors":"Chun-Ming Huang, Chien‐Ming Wu, Chih-Chyau Yang, Wei-De Chien, Shih-Lun Chen, Chi-Shi Chen, J. Wang, C. Wey","doi":"10.1109/ISCAS.2009.5118264","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118264","url":null,"abstract":"A silicon prototyping methodology is presented for Multi-Project System-on-a-Chip (MP-SoC) implementation. A multi-projects platform was created for integrating heterogeneous SoC projects into a single chip. The total silicon prototyping cost of these projects can be greatly reduced by sharing a common platform. To demonstrate the effectiveness of the proposed methodology, a MP-SoC chip was implemented with eleven SoC projects sharing the common platform. The total silicon area is about 37.97mm2 in the TSMC 0.13um CMOS generic logic process technology. Compared with the total chip area 129.39mm2 by implementing these projects separately, the results show that there are 91.42mm2 silicon areas reduced by the MP-SoC platform. In order to verify MP-SoC through silicon prototyping, a system modeling and hardware/ software co-design virtual platform were implemented. A configurable SoC prototyping system, namely CONCORD, is also created as a verification platform for emulating the hardware of MP-SoC before chip being taped out. The CONCORD system provides higher connection flexibility, modularization, and architecture consistence than conventional FPGA systems.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"37 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128438197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Parabolic synthesis methodology implemented on the sine function 对正弦函数实现抛物线综合法
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117733
E. Hertz, P. Nilsson
{"title":"Parabolic synthesis methodology implemented on the sine function","authors":"E. Hertz, P. Nilsson","doi":"10.1109/ISCAS.2009.5117733","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117733","url":null,"abstract":"This paper introduces a parabolic synthesis methodology for implementation of approximations of unary functions like trigonometric functions and logarithms, which are specialized for efficient hardware mapped VLSI design. The advantages with the methodology are, short critical path, fast computation and high throughput enabled by a high degree of architectural parallelism. The feasibility of the methodology is shown by developing an approximation of the sine function for implementation in hardware.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129168136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Fast and area efficient multi-input Muller C-element based on MOS-NDR 基于MOS-NDR的快速高效多输入Muller c元
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118129
J. Núñez, J. Quintana, M. Avedillo
{"title":"Fast and area efficient multi-input Muller C-element based on MOS-NDR","authors":"J. Núñez, J. Quintana, M. Avedillo","doi":"10.1109/ISCAS.2009.5118129","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118129","url":null,"abstract":"A new multi-input Muller C-element based on a MOS-NDR device is proposed in this contribution. This design overcomes some drawbacks of previously proposed structures. A comparison in terms of area, delay and power consumption over another efficient CMOS Muller C-element circuit has been performed, resulting that our structure improves this performance.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124645970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis of reconfigurable tap changing transformer model through analog emulation 通过模拟仿真分析可重构分接变换变压器模型
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118181
J. C. Jiménez, C. Nwankpa
{"title":"Analysis of reconfigurable tap changing transformer model through analog emulation","authors":"J. C. Jiménez, C. Nwankpa","doi":"10.1109/ISCAS.2009.5118181","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118181","url":null,"abstract":"Emulation of power systems is a viable alternative to traditional digital methods as it provides certain advantages such as physically realizable solutions and faster computation times. Accurate analog models of power systems components are required in order to realize an analog computation engine for power systems. Prior research in this field has modeled generators, transmission lines and loads. Other components have significant influence on the power systems, such as tap changing transformers. Effects of tap changing transformers on voltage stability have been a continuing area of research. In this paper, a circuit model design to emulate the behavior of a tap changing transformer is validated. It is important to demonstrate how this reconfigurable analog model may be utilized in load flow studies. Such demonstration is presented by comparing steady-state emulation and simulation results for a test case in which a power system experiences slow gradual changes in load.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129541818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Bulk-driven flipped voltage follower 体积驱动的翻转电压跟随器
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118363
Y. Haga, I. Kale
{"title":"Bulk-driven flipped voltage follower","authors":"Y. Haga, I. Kale","doi":"10.1109/ISCAS.2009.5118363","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118363","url":null,"abstract":"A voltage buffer so-called the bulk-driven flipped voltage follower is presented. This proposal is based on the Flipped Voltage Follower (FVF) technique, but a bulk-driven MOSFET with the replica-biased scheme is utilized for the input device to eliminate the DC level shift. The proposed buffer has been designed and simulated with a 0.35µm CMOS technology. The input current and capacitance of our proposal are 1.5pA and 9.3fF respectively, and with 0.8V peak-to-peak 500kHz input, the total harmonic distortion is 0.5% for a 10pF load. This circuit can operate from a single 1.2V power supply and consumes only 2.5µA.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129638845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
Equivalent circuits for two-fermion four-state quantum systems 二费米子四态量子系统的等效电路
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117813
P. Civalleri, M. Gilli, M. Bonnin
{"title":"Equivalent circuits for two-fermion four-state quantum systems","authors":"P. Civalleri, M. Gilli, M. Bonnin","doi":"10.1109/ISCAS.2009.5117813","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117813","url":null,"abstract":"An equivalent circuit is presented for a quantum system composed of two spin 1/2 particles. Such a circuit shows that the entire dynamics of the system, including single-particle and two-particle annihilation and creation, as well as the single particle transitions between ground and excited states, can be described as the superposition of the variables of two uncoupled resonant circuits.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129904705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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