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2009 IEEE International Symposium on Circuits and Systems最新文献

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An improved publicly detectable watermarking scheme based on scan chain ordering 一种改进的基于扫描链排序的公开可检测水印方案
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117677
Aijiao Cui, Chip-Hong Chang
{"title":"An improved publicly detectable watermarking scheme based on scan chain ordering","authors":"Aijiao Cui, Chip-Hong Chang","doi":"10.1109/ISCAS.2009.5117677","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117677","url":null,"abstract":"This paper proposes an improved version of watermarking scheme at the Design-for-Testability (DfT) stage for VLSI Intellectual Property (IP) Protection. The improved scheme overcomes the weaknesses of previous scan chain watermarking scheme by imposing the extra ordering constraints generated by the IP owner's signature on all scan flip-flops impartially. IP authorship can be publicly authenticated in the field by injecting a given test vector and matching a permuted output response vector against a transformed reference pattern. Both the output response and the reference sequence are related to a pseudorandom sequence generated by a public-key cryptographic algorithm. Experimental results show that the improved method has a low probability of coincidence and low test power overhead.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115381068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Live demonstration: A bio-inspired event-based size and position invariant human posture recognition algorithm 现场演示:一种生物启发的基于事件的大小和位置不变的人体姿势识别算法
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117865
Shoushun Chen, B. Martini, E. Culurciello
{"title":"Live demonstration: A bio-inspired event-based size and position invariant human posture recognition algorithm","authors":"Shoushun Chen, B. Martini, E. Culurciello","doi":"10.1109/ISCAS.2009.5117865","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117865","url":null,"abstract":"We demonstrate a realtime human postures recognition platform. The algorithm employs temporal difference imaging between video sequences as input and then decompose the contour of the active object into vectorial line segments. A scheme based on simplified Line Segment Hausdorff Distance combined with projection histograms is proposed to achieve size and position invariance recognition. Inspired by the hierarchical model of human visual system, the whole classification is described as a coarse to fine procedure. 88% average realtime recognition rate is achieved in the experiment.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115497270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-order fixed denominator IIR VFD filter design 低阶定分母IIR VFD滤波器设计
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117790
H. Kwan, A. Jiang
{"title":"Low-order fixed denominator IIR VFD filter design","authors":"H. Kwan, A. Jiang","doi":"10.1109/ISCAS.2009.5117790","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117790","url":null,"abstract":"A two-stage design method of low-order fixed denominator IIR variable fractional delay (VFD) digital filters is presented in this paper. In the first stage, a set of FIR fractional delay (FD) filters are designed first. Each FIR FD filter design problem is formulated in the peak-constrained weighted least-squares (PCWLS) sense and solved by the projected least-squares (PLS) algorithm. Then, model reduction technique is applied on a time-domain average FIR filter to obtain the fixed denominator. The remaining numerators of the IIR FD filters can be obtained by solving linear equations derived from the orthogonality principle. In the second stage of the design, these FD filter coefficients are to be approximated by polynomial functions of FD. Three sets of filter-examples are given to illustrate the effectiveness of the proposed design method.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115498451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A baseband testbed for uplink mobile MIMO WiMAX communications 用于上行移动MIMO WiMAX通信的基带测试平台
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117874
Yu-Jen Wu, Jung-Mao Lin, Hsin-Yi Yu, Hsi-Pin Ma
{"title":"A baseband testbed for uplink mobile MIMO WiMAX communications","authors":"Yu-Jen Wu, Jung-Mao Lin, Hsin-Yi Yu, Hsi-Pin Ma","doi":"10.1109/ISCAS.2009.5117874","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117874","url":null,"abstract":"In this paper, an efficient advanced RISC machine (ARM)-based system-on-chip (SoC) testbed for a multi-input multi-output orthogonal frequency division multiple access (MIMO-OFDMA) uplink transceiver is presented. To mitigate carrier frequency offset (CFO) and multipath channel impairments, low complexity architecture of an inter-carrier interference (ICI)-cancellation-based CFO estimator and a 2D channel tracker are proposed in the receiver. The proposed transceiver is integrated into the SoC platform and verified by a video codec. Moreover, the proposed testbed provides a fast and configurable HW/SW co-verification prototyping for single-input single-output (SISO)/MIMO-OFDMA systems.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115585746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
An active approach for charge balancing in functional electrical stimulation 功能电刺激中电荷平衡的一种主动方法
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117755
K. Sooksood, T. Stieglitz, M. Ortmanns
{"title":"An active approach for charge balancing in functional electrical stimulation","authors":"K. Sooksood, T. Stieglitz, M. Ortmanns","doi":"10.1109/ISCAS.2009.5117755","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117755","url":null,"abstract":"Charge balancing is a major concern in functional electrical stimulation, since any excess charge accumulation over time leads to electrolysis with electrode dissolution and tissue destruction. This paper presents a new active approach for charge balancing using long-term offset regulation. Therefore, the electrode voltage is briefly monitored after each stimulation cycle and checked if it remains within a predefined voltage range. If not, an offset current is adjusted in order to track the biphasic current mismatch in upcoming stimulations. This technique is compared to a previously introduced active charge balancer and both are verified through experiments on a platinum black electrode in 0.9% saline solution.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115776664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Improving the hardware utilization efficiency of partially parallel LDPC decoder with scheduling and sub-matrix decomposition 利用调度和子矩阵分解提高部分并行LDPC解码器的硬件利用率
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118242
Jie Jin, C. Tsui
{"title":"Improving the hardware utilization efficiency of partially parallel LDPC decoder with scheduling and sub-matrix decomposition","authors":"Jie Jin, C. Tsui","doi":"10.1109/ISCAS.2009.5118242","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118242","url":null,"abstract":"Partially parallel LDPC decoder is commonly used for practical applications due to its good tradeoff between the hardware cost and the throughput. In the partially parallel LDPC decoding architecture, two kinds of processor units are implemented: check node unit (CNU) and variable node unit (VNU). Because of the dependency between two kinds of processor units, the low hardware utilization efficiency (HUE) is one of the design issues for the partially parallel decoding architecture. In order to achieve the optimal hardware utilization efficiency, it is important to determine the order of the rows and columns in the LDPC parity check matrix processed by the processor units. In this paper, we model the scheduling problem as an optimization problem and use simulated annealing to find good solutions for the scheduling. In order to further increase the HUE of the partially parallel decoding architecture, sub-matrix decomposition scheme is proposed. By applying these two schemes, the HUE of some partially parallel decoding implementations can achieve 100%.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115907225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
An adaptive CMOS-based PG-ISFET for pH sensing 基于cmos的pH传感自适应PG-ISFET
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117809
P. Georgiou, C. Toumazou
{"title":"An adaptive CMOS-based PG-ISFET for pH sensing","authors":"P. Georgiou, C. Toumazou","doi":"10.1109/ISCAS.2009.5117809","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117809","url":null,"abstract":"This paper presents a novel CMOS based PG-ISFET (Programmable Gate-Ion Sensitive Field Effect Transistor) and readout for compensation of large threshold voltages observed with ISFETs fabricated in a standard CMOS process. The proposed device uses a capacitively coupled floating gate to allow tunability of its operating point to counteract the presence of trapped charge, thus allowing operation within a tolerable gate voltage range. By using feedback, an adaptive readout has been designed, which allows integration of the device as well as cancellation of reduced sensitivity due to extra capacitance of the programmable gate. Fabricated in a 0.35µm CMOS process, the device can compensate for a variation of up to 14.2V for 1µA using a 3.3V supply.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124280876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A highly efficient interleaved DC-DC converter using coupled inductors in gaas technology gaas技术中使用耦合电感的高效交错DC-DC变换器
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117953
Han Peng, T. Chow, M. Hella
{"title":"A highly efficient interleaved DC-DC converter using coupled inductors in gaas technology","authors":"Han Peng, T. Chow, M. Hella","doi":"10.1109/ISCAS.2009.5117953","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117953","url":null,"abstract":"This paper presents a high power efficiency DC-DC buck converter in Gallium Arsenide technology targeting integrated power amplifier modules. The buck converter adopts an interleaved structure with negatively coupled inductors. Analysis of the effect of coupling on the steady state and transient response of the converter is given. The coupling factor is selected to achieve a maximum power efficiency for a given duty cycle with a minimum penalty on current ripple performance. The DCDC converter is implemented in 0.5µm GaAs pHEMT process and occupies 2.7×2.7mm2 without the output network. It converts 4.5V input to 3.3V output for 1A load current under 250MHz switching frequency with a power efficiency of 86.1%.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"300 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124292005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Estimation of the switching activity in shift-and-add based computations 基于移位加运算的开关活动估计
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118447
K. Johansson, O. Gustafsson, L. DeBrunner
{"title":"Estimation of the switching activity in shift-and-add based computations","authors":"K. Johansson, O. Gustafsson, L. DeBrunner","doi":"10.1109/ISCAS.2009.5118447","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118447","url":null,"abstract":"In this work, we propose a switching activity model for constant multipliers. The model can also be used for other architectures that are composed by full adders. Hence, the proposed model is suitable to be used in power consumption aware design algorithms. An important category is algorithms for the multiple-constant multiplication (MCM) problem. The model is shown to agree well with simulations, especially for carry-save arithmetic.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124318181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Dynamics of the MEMS pulsed digital oscillator with multiple delays in the feedback loop 反馈环路中具有多时延的MEMS脉冲数字振荡器的动力学
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118152
E. Blokhina, O. Feely, M. Domínguez
{"title":"Dynamics of the MEMS pulsed digital oscillator with multiple delays in the feedback loop","authors":"E. Blokhina, O. Feely, M. Domínguez","doi":"10.1109/ISCAS.2009.5118152","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118152","url":null,"abstract":"In this paper we apply methods of nonlinear dynamics to examine the behavior of the pulsed digital oscillator for microelectromechanical systems (MEMS). We study the regions of existence of oscillations and demonstrate the effect on these of including additional delays into the feedback loop.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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