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2009 IEEE International Symposium on Circuits and Systems最新文献

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Arithmetic/logic blocks for fine-grained reconfigurable units 用于细粒度可重构单元的算术/逻辑块
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-06-26 DOI: 10.1109/ISCAS.2009.5118184
G. Cardarilli, L. Nunzio, M. Re
{"title":"Arithmetic/logic blocks for fine-grained reconfigurable units","authors":"G. Cardarilli, L. Nunzio, M. Re","doi":"10.1109/ISCAS.2009.5118184","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118184","url":null,"abstract":"Processing performance of algorithms implemented on conventional processors or DSP can degrade when bit level operations are involved. This degradation is related to the characteristics of logic and arithmetic operators present inside the processors, that are optimized for word level operations. Different methods have been proposed for overcoming this problem. A very interesting method is based on the introduction of specific logic and arithmetic units, jointly to the conventional integer or floating-point units. Due to the great variability of the bit level operations that must be performed, a fixed structure unit is not very suitable for this application. This fact has suggested the introduction of units based on arrays of reconfigurable cells, as the RAM based Look-up Tables. In this paper an alternative reconfigurable cell, specialized for the realization of bit manipulating unit, is described and evaluated. The comparison results show that the proposed solution is very efficient in terms of number of transistors (or silicon area) if compared to a conventional approach based on Look-up Table.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132526885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 2-MHz bi-directional wireless transceiver system for implantable glucose sensors 一种用于植入式葡萄糖传感器的2mhz双向无线收发系统
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117831
Danny Wen-Yaw Chung, A. Albason, A. S. Lou, A. A. Hu
{"title":"A 2-MHz bi-directional wireless transceiver system for implantable glucose sensors","authors":"Danny Wen-Yaw Chung, A. Albason, A. S. Lou, A. A. Hu","doi":"10.1109/ISCAS.2009.5117831","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117831","url":null,"abstract":"This paper describes a bi-directional wireless transceiver system for implantable glucose sensing systems. Command and data will be supplied to the implantable module by RF telemetry utilizing an amplitude shift keying (ASK) modulated 2-MHz carrier frequency. An active uplink transceiver utilizing load shift keying (LSK) as backward data telemetry was designed. Half duplex communication between transceivers at a 2 Kbps data rate was achieved at an effective distance of 3 cm. A capacitor-less internal data receiver was developed measuring at 64.8 µm by 55.9 µm having an average power consumption of 1.15 mW. Implantable receiver was designed using TSMC 0.35 µm 2P4M standard CMOS process.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115336624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Direct design of orthogonal filter banks and wavelets 直接设计正交滤波器组和小波
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117690
Wu-Sheng Lu, T. Hinamoto
{"title":"Direct design of orthogonal filter banks and wavelets","authors":"Wu-Sheng Lu, T. Hinamoto","doi":"10.1109/ISCAS.2009.5117690","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117690","url":null,"abstract":"This paper presents a new method for the design of two-channel conjugate quadrature (CQ) filter banks in which halfband filter and spectrum factorization are not required. Instead, a CQ filter is directly optimized subject to the perfect reconstruction and possibly other constraints (such as number of vanishing moments (VM)). We develop a design strategy in that the solution is approached sequentially with each update confined to within a small vicinity of the current iterate where the problem at hand behaves like a convex one, thus the update can be obtained as a solution of a convex problem. Four design scenarios are considered, namely the least squares designs with or without VM requirement, and equiripple designs with or without VM requirement. The simulation studies demonstrate that the proposed method is reliable to design high-order CQ filters with improved performance.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115437474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A bio-impedance measurement system for portable monitoring of heart rate and pulse wave velocity using small body area 一种用于便携式小体面积心率和脉搏波速度监测的生物阻抗测量系统
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118460
Min-Chang Cho, Jee-Yeon Kim, Seonghwan Cho
{"title":"A bio-impedance measurement system for portable monitoring of heart rate and pulse wave velocity using small body area","authors":"Min-Chang Cho, Jee-Yeon Kim, Seonghwan Cho","doi":"10.1109/ISCAS.2009.5118460","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118460","url":null,"abstract":"Continuous monitoring of cardiovascular system can prevent death and disabilities due to heart failure. In this paper, a bio-impedance measurement system that operates on a small local area of the forearm is presented for portable and continuous monitoring of the heart rate and pulse wave velocity (PWV). The impedance variation caused by the heart pump is measured by analog circuitries that consist of amplifiers, mixers and filters. The overall gain, CMRR, and input impedance of the implemented system using discrete components are 80dB, 72dB and 477kΩ at 100kHz, respectively, which results in a system sensitivity of 21V/Ω. Experimental results show that the heart rate and PWV can be measured by using only 1.5cm × 7cm area of the body. The measured heart rate is in the range of 65∼110 beats/min, and PWV is in 6.51±2.39 (m/s), which fits well with a reference device and normal physiological range. The optimum location for small electrodes in terms of signal quality is also investigated, and the results show that the location at the lower forearm along the radial artery has the best signal quality.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":" 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120829325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 66
Design of class-DE amplifier with linear and nonlinear shunt capacitances for 25 % duty ratio 25%占空比线性和非线性并联de类放大器的设计
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118401
H. Sekiya, R. Miyahara, M. Kazimierczuk
{"title":"Design of class-DE amplifier with linear and nonlinear shunt capacitances for 25 % duty ratio","authors":"H. Sekiya, R. Miyahara, M. Kazimierczuk","doi":"10.1109/ISCAS.2009.5118401","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118401","url":null,"abstract":"The class-E ZVS/ZDS operation within the class-DE amplifier can be easily achieved by adding external shunt capacintaces. This paper presents the analytical expressions for the design of the class-DE amplifier with the shunt capacitances composed of the linear and nonlinear capacitances for the switch-on duty ratio D = 0.25. In the analysis, an equivalent linear shunt capacitance of nonlinear MOSFET output capacitance are defined and derived. The analytical results show good agreement with the experimental ones, which validates our analysis.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121086429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Perspectives and issues in 3D-IC from designers' point of view 从设计师的角度来看3D-IC的观点和问题
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117688
S. Fujita, K. Abe, K. Nomura, S. Yasuda, T. Tanamoto
{"title":"Perspectives and issues in 3D-IC from designers' point of view","authors":"S. Fujita, K. Abe, K. Nomura, S. Yasuda, T. Tanamoto","doi":"10.1109/ISCAS.2009.5117688","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117688","url":null,"abstract":"Recent progress of through-silicon-via (TSV) process is so impressive that everyone can expect real 3D-IC era. The most valuable advantages of 3D-IC is decreasing interconnects. Although analysis of this advantages has been reported in some specific case study, the general theory for quantitative analysis has not been studied. In some cases, the advantage of 3D-IC has been overestimated and much different from that of real chip designs expected. This paper presents the qualitative analysis of general 3D-IC design especially for sub-65nm CMOS generation from designers' point of view. What is understood from this paper is how important IC-design is for 3D-IC and how to gain a big advantage of 3D-IC.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127119075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Location of exons in DNA sequences using digital filters 利用数字滤波器定位DNA序列中的外显子
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118268
Parameswaran Ramachandran, Wu-Sheng Lu, A. Antoniou
{"title":"Location of exons in DNA sequences using digital filters","authors":"Parameswaran Ramachandran, Wu-Sheng Lu, A. Antoniou","doi":"10.1109/ISCAS.2009.5118268","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118268","url":null,"abstract":"A filtering technique for the location of hot spots in proteins proposed recently is applied for the location of exons in DNA sequences. The technique involves conversion of a DNA character sequence into a numerical sequence using the electron-ion interaction potential values and then filtering the numerical sequence using a narrowband bandpass digital filter whose passband is centered at the period-3 frequency, i.e., 2π/3. The strength of the bandpass-filtered signal as a function of nucleotide location is then detected using a lowpass filter. A plot of the signal power versus location reveals the presence of exons as distinct peaks. Simulations have shown that the technique leads to more accurate exon locations than another computational technique based on the short-time discrete Fourier transform. Furthermore, the amount of computation required is reduced by as much as 97 percent thereby rendering the technique suitable for the processing of long DNA sequences, even complete genomes.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124773451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
An automated algorithm to generate stream programs 生成流程序的自动算法
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118053
L. Gao, Gaurav Mittal, David Zaretsky, D. Schonfeld, P. Banerjee
{"title":"An automated algorithm to generate stream programs","authors":"L. Gao, Gaurav Mittal, David Zaretsky, D. Schonfeld, P. Banerjee","doi":"10.1109/ISCAS.2009.5118053","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118053","url":null,"abstract":"With the proliferation of reconfigurable systems and flexible memory architectures, there has been intense interest in stream systems. While the existing stream systems require the programs to be written using special models, this paper demonstrates an approach to automatically generate stream programs from existing applications written for non-stream scalar processors. As a part of this approach, we provide a new comparison methodology and an algorithm to automatically generate stream descriptions. A second algorithm identifies processing kernels that can be pipelined. We demonstrate our results on an FPGA based platform.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125927107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reduction of test power and data volume in BIST scheme based on scan slice overlapping 基于扫描片重叠的BIST方案中测试功率和数据量的降低
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5118368
Zhou Bin, Ye Yi-zheng, Wu Xin-chun, Li Zhao-lin
{"title":"Reduction of test power and data volume in BIST scheme based on scan slice overlapping","authors":"Zhou Bin, Ye Yi-zheng, Wu Xin-chun, Li Zhao-lin","doi":"10.1109/ISCAS.2009.5118368","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118368","url":null,"abstract":"In order to further reduce test data storage and test power of deterministic BIST based on LFSR reseeding and scan slice overlapping scheme, two optimization algorithms are proposed. One algorithm is to reorder scan cell by random exchanging two scan cells considering layout constraint in every loop. If both the number of specified bits and the number of overlapping blocks after exchanging operation are decreased, the exchanging operation is kept, otherwise the exchanging operation is ignored. The other algorithm is to partition test patterns by selecting the scan slice with most specified bits as the first scan slice of the current overlapping block. In this way, the partition which can lead to the minimal number of overlapping blocks and the minimal number of specified bits can be always achieved. Combining the proposed algorithms, test power and even test data storage can be significantly reduced. Experimental results indicate that the proposed method significantly reduces the switching activity and test data storage by 72%–92% and 54%–91%, respectively.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"263 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126053033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
On the distributions of the relative phase of complex wavelet coefficients 复小波系数相对相位分布的研究
2009 IEEE International Symposium on Circuits and Systems Pub Date : 2009-05-24 DOI: 10.1109/ISCAS.2009.5117802
An P. N. Vo, S. Oraintara
{"title":"On the distributions of the relative phase of complex wavelet coefficients","authors":"An P. N. Vo, S. Oraintara","doi":"10.1109/ISCAS.2009.5117802","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117802","url":null,"abstract":"In this paper, the probability distributions of relative phase are studied. We proposed von Mises and wrapped Cauchy for the probability density function (pdf) of the relative phase in complex wavelet domain. The maximum-likelihood method is used to estimate the two parameters of von Mises and wrapped Cauchy. We demonstrate that the von Mises and wrapped Cauchy fit well with real data obtained from various real images including texture images as well as natural images. The von Mises and wrapped Cauchy models are compared, and the simulation results show that the wrapped Cauchy fits well with the peaky and heavy-tailed pdf of the relative phase and the von Mises fits well with the pdf which is in Gaussian shape. For most of the test images, the wrapped Cauchy model is more accurate than the von Mises, when images are decomposed by different complex wavelet transforms including dual-tree complex wavelet (DTCWT), pyramidal dual-tree directional filter bank (PDTDFB) and a modified version of curvelet.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"43 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126071887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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