C. Chan, Weiwei Shi, K. Pun, L. Leung, K. Leung, O. Choy
{"title":"A Low-power signal processing front-end and decoder for UHF passive RFID transponders","authors":"C. Chan, Weiwei Shi, K. Pun, L. Leung, K. Leung, O. Choy","doi":"10.1109/ISCAS.2009.5118072","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118072","url":null,"abstract":"In this paper, a low-power signal processing front-end and PIE decoder for use in UHF RFID passive transponders is presented. By merging with the decoder, the clock generator does not need to drive a large loading capacitor. Therefore, its power consumption can be greatly reduced. In addition, the ring oscillator of the generator was designed for low sensitivity to supply voltage variation and low power consumption. Fabricated in a 0.13-µm CMOS process, the measured power consumption consumes only 850nW.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133496899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automatic model refinement of GmC integrators for high-level simulation of continuous-time Sigma-Delta modulators","authors":"M. Vasilevski, H. Aboushady, M. Louërat","doi":"10.1109/ISCAS.2009.5118376","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118376","url":null,"abstract":"A ΣΔ GmC integrator refinement flow is presented. The classically simplified GmC integrator small-signal model was upgraded to be extremely accurate by considering the complete transistor small-signal model. A circuit-level knowledge-based tool was used to execute the designer defined sizing procedure and to extract small signal parameters. By associating the symbolic transfer function to small-signal parameters, the flow, entirely implemented with C++, is able to compute poles and zeros to permit precise behavioral simulations. A 2nd order ΣΔ modulator was chosen to visualize performance degradations while the specifications were not achievable.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133688629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Noise reduction for low-power broadband filtering","authors":"Renfei Liu, K. Parhi","doi":"10.1109/ISCAS.2009.5117930","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117930","url":null,"abstract":"Supply voltage overscaling (VOS) has been studied recently for the design of low power finite impulse response (FIR) filters, where estimation-based noise reduction schemes are used for reducing the computational noise. When broadband filters are concerned, which are widely used in the scenario of high speed communication such as frequency-division multiplexed (FDM) systems, existing noise reduction schemes fail due to the relatively low dependency among broadband filter output samples. In this paper, a novel noise reduction scheme is proposed for broadband filters, which is the first implementation-independent scheme that can effectively reduce the noise due to both voltage overscaling and environmental fluctuations. Simulation results show that the proposed scheme achieves 7–27 dB performance gain while achieving 10.33%–51.74% power saving.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"28 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133286995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and analysis of a current-reuse transmitter for ultra-low power applications","authors":"Le Zheng, Hsin-Cheng Yao, F. Tzeng, P. Heydari","doi":"10.1109/ISCAS.2009.5118006","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118006","url":null,"abstract":"A CMOS current-reuse transmitter for ultra-low power (ULP) applications is presented. It can provide up to 10.2dBm of output power with a total efficiency of 30% at 2.4GHz. By utilizing the stacking technique, the average current of a class-E power amplifier is reused by the accompanying VCO and an optional RX block. The breakdown issue associated with the class-E PA is mitigated. A detailed analysis of the current-reuse structure is demonstrated. Practical design issues are discussed and appropriate design guidelines are provided.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132197673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamical equivalencing of large-scale power systems using Second-Order Arnoldi algorithms","authors":"C. Chu, Hung-Chi Tsai, M. Lai","doi":"10.1109/ISCAS.2009.5118177","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118177","url":null,"abstract":"This paper proposes a technique for constructing dynamical equivalent networks of large-scale linearized power systems by using the Second-Order Arnoldi (SOAR) algorithm. Since the power system can be described by second-order swing equations, it is desired to construct a reduced-order model which can preserve its second-order structure. Inspired by the SOAR algorithm for single input systems, we will extend it with considering multiple inputs. Both block Arnoldi methods and global Arnoldi methods are investigated. System data of the reduced second-order system are obtained by the congruence transformation. Simulations about 50-machine power systems are performed to demonstrate the accuracy of the dynamical equivalent networks.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132291362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Realization of 3-D separable-denominator digital filters with very low l2-sensitivity","authors":"T. Hinamoto, O. Tanaka, Wu-Sheng Lu","doi":"10.1109/ISCAS.2009.5117750","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117750","url":null,"abstract":"This paper investigates the problem of reducing the deviation from a desired transfer function caused by the coefficient quantization errors of a three-dimensional (3-D) separable-denominator digital filter. First, a 3-D transfer function with separable denominator is represented with the cascade connection of three one-dimensional (1-D) transfer functions by applying a minimal decomposition technique. Next, the multiinput multi-output (MIMO) 1-D transfer function located in the middle of the cascade connection is realized by a minimal state-space model and then the l2/l2-sensitivity of the model is analyzed. Third, a technique for the optimal synthesis of the minimal state-space model is developed so as to minimize the l2-sensitivity subject to l2-scaling constraints. Finally, a numerical example is given to demonstrate the validity and effectiveness of the proposed technique.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128863527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On the use of a UML-Based HW/SW Co-Design Platform for reconfigurable cryptographic systems","authors":"Chun-Hsian Huang, Pao-Ann Hsiung","doi":"10.1109/ISCAS.2009.5118239","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118239","url":null,"abstract":"In this work, we use our proposed UML-Based HW/SW Co-Design Platform (UCoP) to implement a reconfigurable cryptographic system for network multimedia applications. The UCoP is categorized into three reusable models, including software application, hardware configuration and system management models. Through the use of the reusable models, the proposed dynamically partially reconfigurable system can be easily implemented in UCoP. Furthermore, the direct interaction with the real system architecture in UCoP is very helpful to designers in validating and analyzing system correctness and performance at a high-level, which can significantly reduce system development efforts. We compare the use of UCoP with a lowerbound estimation method by implementing a network multimedia application with the data encryption/decryption. According to our experiment results, we can clearly see how UCoP plays a key role in helping designers to develop dynamically partially reconfigurable systems with hard real-time constraints.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134465670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"NMOS-only Class-D output stages based on charge pump architectures","authors":"Steven Maughan, R. Henderson","doi":"10.1109/ISCAS.2009.5117973","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117973","url":null,"abstract":"An NMOS only Class-D output driver which uses charge pump techniques in a low voltage CMOS technology is presented. Compared to conventional Class-D output stages, the given implementation shows a gate area reduction of 45%, resulting in efficiency improvements. The circuit has been simulated in a 0.13µm process and is implemented using 3.3V I/O devices. The structure does not violate any gate-oxide reliability rules.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134487673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yusuke Tsugita, K. Ueno, T. Asai, Y. Amemiya, T. Hirose
{"title":"On-chip PVT compensation techniques for low-voltage CMOS digital LSIs","authors":"Yusuke Tsugita, K. Ueno, T. Asai, Y. Amemiya, T. Hirose","doi":"10.1109/ISCAS.2009.5118068","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5118068","url":null,"abstract":"An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133799691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fast-locking and wide-range reversible SAR DLL","authors":"Lei Wang, Leibo Liu, Hongyi Chen","doi":"10.1109/ISCAS.2009.5117925","DOIUrl":"https://doi.org/10.1109/ISCAS.2009.5117925","url":null,"abstract":"A reversible successive approximation register (RSAR) controlled all-digital delay-locked loop (ADDLL) is proposed to achieve fast-lock and wide range operation. The modified binary search algorithm of RSAR scheme is presented. With improved RSAR control-circuits, it could achieve adaptive bandwidth in wide range operation and eliminate the dead lock problem of conventional SAR DLL. The maximal lock-in cycles are reduced down to 42 for the 11-bit RSAR DLL, and its frequency range is from 30 MHz to 1 GHz in post layout simulation. The layout is done in SMIC 0.13 um CMOS technology, and an active area of 0.2 mm by 0.1 mm is occupied.","PeriodicalId":388394,"journal":{"name":"2009 IEEE International Symposium on Circuits and Systems","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-05-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127898290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}