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IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.最新文献

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Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme 基于软阈值多层检测方案的鲁棒决策反馈均衡器设计
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363035
Chih-Hsiu Lin, A. Wu
{"title":"Robust decision feedback equalizer design using soft-threshold-based multi-layer detection scheme","authors":"Chih-Hsiu Lin, A. Wu","doi":"10.1109/SIPS.2004.1363035","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363035","url":null,"abstract":"Most cost-effective DFE implementations suffer from the phenomenon of error propagation, which degrades its bit error rate (BER) performance. To solve this problem, we proposes a soft-threshold-based multi-layer DFE (STM-DFE) technique to reduce the BER. It costs very low hardware overhead compared to the conventional DFE. The key idea is to define a reliable/unreliable region in the DFE algorithm. When the output of the equalizer is in the unreliable region, the STM-DFE does not make a decision on the current symbol, but outputs a log-likelihood ratio to the next symbol. This process continues until the decision becomes reliable, or reaches the maximum stage number. The optimal threshold value between the reliable and unreliable region is analyzed in close-form. Simulation results show that the proposed scheme can efficiently reduce the burst error length (BEL) as well as the BER.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124883690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power optimization of a reconfigurable FIR-filter 可重构fir滤波器的功率优化
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363070
H. Bruce, R. Veljanovski, V. Owall, J. Singh
{"title":"Power optimization of a reconfigurable FIR-filter","authors":"H. Bruce, R. Veljanovski, V. Owall, J. Singh","doi":"10.1109/SIPS.2004.1363070","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363070","url":null,"abstract":"This paper describes power optimization techniques applied to a reconfigurable digital finite impulse response (FIR) filter used in a Universal Mobile Telephone Service (UMTS) mobile terminal. Various methods of optimization for implementation were combined to achieve low cost in terms of power consumption. Each optimization method is described in detail and is applied to the reconfigurable filter. The optimization methods have achieved a 78.8% reduction in complexity for the multipliers in the FIR structure. A comparison of synthesized RTL models of the original and the optimized architectures resulted in a 27% reduction in look-up tables when targeted for the Xilinx Virtex II Pro field programmable gate array (FPGA). An automated method for transformation of coefficient multipliers into bit-shifts is also presented.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122520176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A turbo decoder architecture with scalable parallelism 具有可扩展并行性的涡轮解码器架构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363066
N. Engin
{"title":"A turbo decoder architecture with scalable parallelism","authors":"N. Engin","doi":"10.1109/SIPS.2004.1363066","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363066","url":null,"abstract":"A scalable, programmable turbo decoder architecture is presented in this paper. The starting point is a comparison of the existing techniques on the basis of scalability, area and power consumption. The results from these comparisons lead to a hybrid technique on which our architecture concept is based. The architecture consists of clusters, each of which is a VLIW architecture. The upsizing is possible by adding a cluster and dividing the two data memories into banks. The window size is chosen according to the number of banks, to prevent conflicts. At the end of the paper, a short evaluation of the architecture is presented.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"166 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123559432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Design of a lattice decoder for MIMO systems in FPGA 基于FPGA的MIMO系统点阵解码器设计
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363019
Jing Ma, Xinming Huang
{"title":"Design of a lattice decoder for MIMO systems in FPGA","authors":"Jing Ma, Xinming Huang","doi":"10.1109/SIPS.2004.1363019","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363019","url":null,"abstract":"Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using an FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7 Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129672035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Node prefetch prediction in dataflow graphs 数据流图中的节点预取预测
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363068
N.G. Petersen, M. R. Wójcik
{"title":"Node prefetch prediction in dataflow graphs","authors":"N.G. Petersen, M. R. Wójcik","doi":"10.1109/SIPS.2004.1363068","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363068","url":null,"abstract":"Dataflow languages provide a high-level description that can expose inherent parallelism in many applications. This high level description can be applied to automatically create efficient code and schedules based on patterns in the dataflow graphs and knowledge of the target architecture. When targeting a dataflow graph to custom hardware, it is sometimes advantageous to share nodes with similar functionality to save silicon. Any state information associated with the caller of the shared node must be stored and subsequently loaded upon firing. If prediction logic can predict which caller of a shared node is next, the associated state information can be prefetched while other nodes of the graph are executing. While some applications can be entirely scheduled at compile time, many multi- channel measurement and control applications require some degree of dynamic scheduling. This paper's key contribution is a lightweight call prediction unit with 100% prediction accuracy given a runtime-determined periodic calling schedule. While applications are varied, we show a 33% speedup in a filtering application possible in wireless ad hoc networks.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124628403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Synthesis and high level optimisation of multidimensional dataflow actor networks on FPGA 基于FPGA的多维数据流参与者网络的综合与高级优化
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363043
J. McAllister, R. Woods, R. Walke, D. Reilly
{"title":"Synthesis and high level optimisation of multidimensional dataflow actor networks on FPGA","authors":"J. McAllister, R. Woods, R. Walke, D. Reilly","doi":"10.1109/SIPS.2004.1363043","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363043","url":null,"abstract":"This paper presents a new dataflow graph based approach for modelling, rapidly implementing, and performing high level optimization of embedded systems including dedicated pipelined hardware components. This overcomes problems with current approaches which cannot achieve both pipelined circuit implementation and flexibility for high level optimization. A new dataflow modeling technique is presented, in conjunction with an enhanced component network synthesis approach. This technique is applied to a normalized lattice filter example, demonstrating the capability for significant circuit performance improvements, a more intelligent directed synthesis flow and increased implementation flexibility.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Efficient hardware realization of IRA code decoders IRA译码器的高效硬件实现
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363064
F. Kienle, N. Wehn
{"title":"Efficient hardware realization of IRA code decoders","authors":"F. Kienle, N. Wehn","doi":"10.1109/SIPS.2004.1363064","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363064","url":null,"abstract":"Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of low-density parity-check (LDPC) codes and can even outperform the recently introduced turbo-codes of current communication standards. Implementation complexities like area and achievable throughput of these channel coding schemes have a major impact on the decisions of standardization committees. In this paper, we investigate implementation issues of IRA codes and analyze the strong interdependency of code performance and architectural dependencies, like throughput and area. We present an architecture template which is capable of decoding hardware optimized IRA codes which can outperform turbo-codes. We demonstrate this new approach through instances synthesized in a 0.13 /spl mu/m technology.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"63 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131830583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Power and content aware video encoding for video communication over wireless networks 用于无线网络上视频通信的功率和内容感知视频编码
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363061
Yongshang Liang, I. Ahmad
{"title":"Power and content aware video encoding for video communication over wireless networks","authors":"Yongshang Liang, I. Ahmad","doi":"10.1109/SIPS.2004.1363061","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363061","url":null,"abstract":"In the highly versatile next-generation wireless networks, a fundamental problem is how to manage power consumption efficiently while preserving high quality performance. The paper addresses power-and-content-aware video encoding in pervasive wireless/mobile environments. We formulate the problem of video quality maximization while preserving the battery power of the underlying device as an optimization problem. This is equivalent to minimizing both the power consumption and video distortion simultaneously. Based on a complexity scalable video coding architecture and content aware adjustment, we propose a software based compression scheme. We call the proposed encoder active because it best uses its bits and power and tunes its parameters accordingly. The preliminary results show that the encoder determines a suitable configuration according to the coding environment in order to save power and maintain well-perceived video quality.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121198775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC) 迈向MPEG-4第10部分片上系统:基于上下文的自适应变长编码(CAVLC)的VLSI原型
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363062
I. Amer, Wael Badawy, G. Jullien
{"title":"Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC)","authors":"I. Amer, Wael Badawy, G. Jullien","doi":"10.1109/SIPS.2004.1363062","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363062","url":null,"abstract":"The paper presents a VLSI prototype for context-based adaptive variable length coding (CAVLC). This scheme is a part of the lossless compression process in the MPEG-4 Part 10 standard. It is applied to the quantized transform coefficients of the luminance component during the entropy coding process. In combination with previous transformations and quantizations, it can result in significantly increased compression ratio. The developed architecture is prototyped and simulated using ModelSim 5.4/spl reg/. It is synthesized using Synplify Pro 7.1/spl reg/. The results show that the architecture satisfies the real-time constraints required by different digital video applications.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116972150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Rapid MIMO-OFDM software defined radio system prototyping 快速MIMO-OFDM软件定义的无线电系统原型
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363046
Amit Gupta, A. Forenza, Robert W. Heath
{"title":"Rapid MIMO-OFDM software defined radio system prototyping","authors":"Amit Gupta, A. Forenza, Robert W. Heath","doi":"10.1109/SIPS.2004.1363046","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363046","url":null,"abstract":"Combining MIMO with OFDM, it is possible to significantly reduce receiver complexity as OFDM greatly simplifies equalization at the receiver. MIMO-OFDM is currently being considered for a number of developing wireless standards; consequently, the study of MIMO-OFDM in realistic environments is of great importance. This paper describes an approach for prototyping a MIMO-OFDM systems using a flexible software defined radio (SDR) system architecture in conjunction with commercially available hardware. An emphasis on software permits a focus on algorithm and system design issues rather than implementation and hardware configuration. The penalty of this flexibility, however, is that the ease of use comes at the expense of overall throughput. To illustrate the benefits of the proposed architecture, applications to MIMO-OFDM system prototyping and preliminary MIMO channel measurements are presented. A detailed description of the hardware is provided along with downloadable software to reproduce the system.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127448176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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