{"title":"Design of a lattice decoder for MIMO systems in FPGA","authors":"Jing Ma, Xinming Huang","doi":"10.1109/SIPS.2004.1363019","DOIUrl":null,"url":null,"abstract":"Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using an FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7 Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.2004.1363019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using an FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7 Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.