Design of a lattice decoder for MIMO systems in FPGA

Jing Ma, Xinming Huang
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引用次数: 2

Abstract

Hardware implementation of lattice decoding algorithms becomes a challenging task as the complexity of MIMO systems increases. This paper presents the design and implementation of a Schnorr-Euchner strategy based lattice decoder using an FPGA. This lattice decoding algorithm has high data dependency during the iterative closest lattice point search procedures. The parallelism of the algorithm is explored and efficient hardware architectures are developed with the decoding function on FPGA and the data preprocessing on DSP. The system prototype of the decoder shows that it supports 2.7 Mbits/s data rate on a Virtex2-1000 FPGA, and is about 4 times faster than a DSP-based lattice decoder. The bit error rate (BER) performance is also tested and verified with software simulation.
基于FPGA的MIMO系统点阵解码器设计
随着MIMO系统复杂性的增加,晶格解码算法的硬件实现成为一项具有挑战性的任务。本文介绍了一种基于Schnorr-Euchner策略的栅格解码器的设计与实现。该算法在迭代最接近格点搜索过程中具有较高的数据依赖性。探讨了算法的并行性,开发了高效的硬件架构,在FPGA上实现解码功能,在DSP上实现数据预处理。解码器的系统原型表明,它在Virtex2-1000 FPGA上支持2.7 Mbits/s的数据速率,比基于dsp的晶格解码器快4倍左右。通过软件仿真测试和验证了系统的误码率性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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