A turbo decoder architecture with scalable parallelism

Abstract

A scalable, programmable turbo decoder architecture is presented in this paper. The starting point is a comparison of the existing techniques on the basis of scalability, area and power consumption. The results from these comparisons lead to a hybrid technique on which our architecture concept is based. The architecture consists of clusters, each of which is a VLIW architecture. The upsizing is possible by adding a cluster and dividing the two data memories into banks. The window size is chosen according to the number of banks, to prevent conflicts. At the end of the paper, a short evaluation of the architecture is presented.