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IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.最新文献

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Complexity reduction of the decoders for interleaved trellis coded modulation schemes for 10 gigabit Ethernet over copper 10千兆以太网交错网格编码调制方案解码器的复杂性降低
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363037
Y. Gu, K. K. Parhi
{"title":"Complexity reduction of the decoders for interleaved trellis coded modulation schemes for 10 gigabit Ethernet over copper","authors":"Y. Gu, K. K. Parhi","doi":"10.1109/SIPS.2004.1363037","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363037","url":null,"abstract":"10GBASE-T (10 gigabit Ethernet over unshielded twisted pairs) will probably use a 10-level pulse amplitude modulation (PAM10) as well as a 4D trellis code similar to the one in 1000BASE-T (1000 megabit Ethernet over copper medium). The trellis code can be used in a conventional way as in 1000BASE-T, but the corresponding decoder with a long critical path needs to operate at 833 MHz. To solve the problem, two interleaved trellis coded modulation schemes were proposed in our previous work. The inherent decoding speed requirements can be relaxed by factors of 4 and 2, respectively. Due to intersymbol interference (ISI), the branch metric units in the decoders corresponding to the two interleaved modulation schemes are much more complicated than those in the conventional decoder. Thus, this paper considers the problem of complexity reduction of the decoders for the two interleaved modulation schemes. Two complexity reduction schemes are proposed. Simulation results show that the performance loss due to complexity reduction is negligible.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126114370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel pipelined fast Fourier transform architecture for double rate OFDM systems 一种新的双速率OFDM系统的流水线快速傅里叶变换体系结构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363016
Hsin-Lei Lin, Hongchin Lin, Yu-Chuan Chen, R. Chang
{"title":"A novel pipelined fast Fourier transform architecture for double rate OFDM systems","authors":"Hsin-Lei Lin, Hongchin Lin, Yu-Chuan Chen, R. Chang","doi":"10.1109/SIPS.2004.1363016","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363016","url":null,"abstract":"A high throughput fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) processor for double-rate wireless LAN, based on double-rate OFDM communication systems, is proposed. It is an efficiently pipelined radix-2 FFT architecture, which doubles the throughput with significant hardware reduction. The utilization rate of multipliers and the processing elements reach 100%. The core size is 10 mm/sup 2/ with a power consumption of 208 mW at 20 MHz for data inputs with 15-bit word length, using 0.35 /spl mu/m IP4M CMOS technology.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125561366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A low power localization architecture and system for wireless sensor networks 一种无线传感器网络的低功耗定位体系结构和系统
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363030
T. Karalar, S. Yamashita, M. Sheets, J. Rabaey
{"title":"A low power localization architecture and system for wireless sensor networks","authors":"T. Karalar, S. Yamashita, M. Sheets, J. Rabaey","doi":"10.1109/SIPS.2004.1363030","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363030","url":null,"abstract":"Localization (or locationing) is a central concern for ubiquitous self-configuring sensor networks. The implementation of a distributed, least-squares-based localization algorithm is presented. Low power and energy dissipation are key requirements for sensor networks. As part of the sensor network, the localization system must also conform to these requirements. An ultra-low-power and dedicated hardware implementation of the localization system is therefore presented. The cost of fixed-point implementation is also investigated. The design is implemented in a 0.13 /spl mu/ CMOS process. It dissipates 1.7 mW of active power and 0.122 nJ/op of active energy with a silicon area of 0.55 mm/sup 2/. The mean calculated location error due to fixed-point implementation is shown to be 6%.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133757970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Platform-based MPEG-4 video encoder SOC design 基于平台的MPEG-4视频编码器SOC设计
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363058
Yung-Chi Chang, Wei-Min Chao, Liang-Gee Chen
{"title":"Platform-based MPEG-4 video encoder SOC design","authors":"Yung-Chi Chang, Wei-Min Chao, Liang-Gee Chen","doi":"10.1109/SIPS.2004.1363058","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363058","url":null,"abstract":"An MPEG-4 video coding SOC design is presented. We adopt a platform-based architecture with an embedded RISC core and efficient memory organization. A motion estimator supporting predictive diamond search and spiral full search is implemented to provide a compromise between compression performance and design cost. The proposed data reuse scheme reduces the required memory access bandwidth. Several key modules are integrated into an efficient platform in a hardware/software codesign fashion. The cost-efficient video encoder SOC consumes 256.8 mW at 40 MHz and achieves real-time encoding of 30 CIF (352/spl times/288) frames per second.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123907092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Reduced-complexity sphere decoding via detection ordering for linear multi-input multi-output channels 基于检测排序的线性多输入多输出信道的降低复杂度球解码
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363020
Yongtao Wang, K. Roy
{"title":"Reduced-complexity sphere decoding via detection ordering for linear multi-input multi-output channels","authors":"Yongtao Wang, K. Roy","doi":"10.1109/SIPS.2004.1363020","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363020","url":null,"abstract":"Sphere decoding is a powerful approach for maximum-likelihood (ML) detection over Gaussian multi-input multi-output (MIMO) linear channels. We propose a new detection ordering approach, which minimizes the corresponding diagonal element of the upper-triangular matrix R over all possible column permutations in each step of the QR decomposition. Compared with the previously proposed V-BLAST ZF-DFE ordering approach, our approach has two major advantages: (1) it is efficiently embedded in the QR decomposition with a small computational overhead, rendering itself suitable for fast-varying channels, while the V-BLAST ZF-DFE ordering is not suitable for fast-varying channels since it incurs large computation overhead; (2) the sphere decoder with our proposed detection ordering achieves 17%-69% and 9%-59% reductions in the number of multiplications and the number of additions, respectively, in comparison to that with the V-BLAST ZF-DFE ordering.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128018995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An efficient reformulation based VLSI architecture for adaptive Viterbi decoding in wireless applications 无线应用中自适应维特比译码的高效重构VLSI架构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363050
Y. Gang, T. Arslan, A. Erdogan
{"title":"An efficient reformulation based VLSI architecture for adaptive Viterbi decoding in wireless applications","authors":"Y. Gang, T. Arslan, A. Erdogan","doi":"10.1109/SIPS.2004.1363050","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363050","url":null,"abstract":"New trends in wireless communication systems has dictated the need for dynamical adaptation of communication systems in order to suit environmental requirements. The authors present a reformulation based VLSI architecture for threshold selection for adaptive Viterbi decoding in wireless applications. Through reformulation of the adaptive Viterbi algorithm, the compare operation for threshold selection in the add compare select (ACS) unit is simplified from variable based to constant based and the width of the path metric is reduced. The reformulated architecture results in a significant reduction of hardware complexity in both standard cell and look up table (LUT) technologies. The paper describes the reformulation technique, its VLSI architecture for adaptive Viterbi decoding and its implementations in both ASIC and FPGA technologies. We also demonstrate that in addition to significant reduction in data path complexity, there is also a 25% to 47% storage reduction in the path metric memory unit (PMU).","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117197642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Oversampled channelized receiver for transmitted reference UWB system in the presence of narrowband interference 存在窄带干扰时用于传输参考UWB系统的过采样信道化接收机
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363023
Lei Feng, W. Namgoong
{"title":"Oversampled channelized receiver for transmitted reference UWB system in the presence of narrowband interference","authors":"Lei Feng, W. Namgoong","doi":"10.1109/SIPS.2004.1363023","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363023","url":null,"abstract":"An oversampled frequency channelized receiver for UWB radio in a transmitted reference (TR) system is presented. Unlike previous work that assumes a white input noise, this paper includes the effects of the automatic gain controller (AGC) and the analog-to-digital converter (ADC) when large narrowband interference (NBI) is present. A detection method for the frequency channelized receiver when input noise is colored in the TR UWB system is proposed. The proposed receiver significantly outperforms the full band receiver.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"216 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123068988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A low complexity algorithm for proportional resource allocation in OFDMA systems OFDMA系统中资源比例分配的一种低复杂度算法
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363015
I. Wong, Zukang Shen, B. Evans, J. Andrews
{"title":"A low complexity algorithm for proportional resource allocation in OFDMA systems","authors":"I. Wong, Zukang Shen, B. Evans, J. Andrews","doi":"10.1109/SIPS.2004.1363015","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363015","url":null,"abstract":"Orthogonal frequency division multiple access (OFDMA) basestations allow multiple users to transmit simultaneously on different subcarriers during the same symbol period. This paper considers basestation allocation of subcarriers and power to each user to maximize the sum of user data rates, subject to constraints on total power, bit error rate, and proportionality among user data rates. Previous allocation methods have been iterative nonlinear methods suitable for offline optimization. In the special high subchannel SNR case, an iterative root-finding method has linear-time complexity in the number of users and N log N complexity in the number of subchannels. We propose a non-iterative method that is made possible by our relaxation of strict user rate proportionality constraints. Compared to the root-finding method, the proposed method waives the restriction of high subchannel SNR, has significantly lower complexity, and in simulation, yields higher user data rates.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130879958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 345
Montgomery modular multiplication architecture for public key cryptosystems 用于公钥密码系统的Montgomery模乘法体系结构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363075
M. McLoone, C. McIvor, J. McCanny
{"title":"Montgomery modular multiplication architecture for public key cryptosystems","authors":"M. McLoone, C. McIvor, J. McCanny","doi":"10.1109/SIPS.2004.1363075","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363075","url":null,"abstract":"This paper describes a novel hardware architecture of the coarsely integrated hybrid scanning (CIHS) algorithm which performs Montgomery modular multiplication. The CIHS algorithm integrates the multiplication and reduction steps involved in modular multiplication. When implemented on a Virtex XC2VP50 device, the architecture can perform 128-bit modular multiplication at a data-rate of 160 Mbit/s and 256-bit modular multiplication at 216 Mbit/s. To the authors' knowledge, these are the first performance figures for a hardware CIHS algorithm architecture to be reported in the literature. A methodology for generating Montgomery multiplication test vectors is also described.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129056433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An energy-efficient OFDM ultra-wideband digital radio architecture 一种节能的OFDM超宽带数字无线电架构
IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004. Pub Date : 2004-12-06 DOI: 10.1109/SIPS.2004.1363051
Sung-Won Chung, Seung-Yoon Lee, Kyu-Ho Park
{"title":"An energy-efficient OFDM ultra-wideband digital radio architecture","authors":"Sung-Won Chung, Seung-Yoon Lee, Kyu-Ho Park","doi":"10.1109/SIPS.2004.1363051","DOIUrl":"https://doi.org/10.1109/SIPS.2004.1363051","url":null,"abstract":"We propose an energy efficient architecture, utilizing peak-to-average power ratio (PAR) information in both transmitter and receiver side. It is identified that the energy consumption of digital-to-analog (D/A) and analog-to-digital (A/D) conversion is the most critical bottleneck in realizing energy efficient digital radios with high data rate. Therefore, our transmitter reduces requantization noise in D/A conversion by digital OFDM symbol up-scaling before D/A conversion and analog OFDM symbol inverse-scaling after D/A conversion. Our receiver reduces quantization noise in A/D conversion by fine tracking automatic gain control (AGC) for each OFDM symbol, after coarse AGC is performed. The proposed architecture reduces a power consumption of D/A and A/D conversion by up to 24% while providing the same performance as the conventional one.","PeriodicalId":384858,"journal":{"name":"IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122011733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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