Montgomery modular multiplication architecture for public key cryptosystems

Abstract

This paper describes a novel hardware architecture of the coarsely integrated hybrid scanning (CIHS) algorithm which performs Montgomery modular multiplication. The CIHS algorithm integrates the multiplication and reduction steps involved in modular multiplication. When implemented on a Virtex XC2VP50 device, the architecture can perform 128-bit modular multiplication at a data-rate of 160 Mbit/s and 256-bit modular multiplication at 216 Mbit/s. To the authors' knowledge, these are the first performance figures for a hardware CIHS algorithm architecture to be reported in the literature. A methodology for generating Montgomery multiplication test vectors is also described.