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Buffer sizing for delay uncertainty induced by process variations 由工艺变化引起的延迟不确定性的缓冲大小
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399706
D. Velenis, Ramyashree Sundaresha, E. Friedman
{"title":"Buffer sizing for delay uncertainty induced by process variations","authors":"D. Velenis, Ramyashree Sundaresha, E. Friedman","doi":"10.1109/ICECS.2004.1399706","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399706","url":null,"abstract":"Controlling the delay of a signal in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high performance synchronous circuits. The effects of device parameter variations on the signal propagation delay of a CMOS buffer are described in this paper. It is shown that delay uncertainty is introduced due to variations in the current flow through a buffer. In addition, the variations in the parasitic resistance and capacitance of an interconnect line also affect the buffer delay. A design methodology that reduces the delay uncertainty of signals propagating along buffer-driven interconnect lines is presented. The proposed methodology increases the current flow sourced by a buffer to reduce the sensitivity of the delay on device and interconnect parameter variations.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"105 1","pages":"415-418"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76418128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Fast high-level fault simulator 快速高级故障模拟器
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399748
S. Deniziak, K. Sapiecha
{"title":"Fast high-level fault simulator","authors":"S. Deniziak, K. Sapiecha","doi":"10.1109/ICECS.2004.1399748","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399748","url":null,"abstract":"A new fast fault simulation technique is presented for calculating fault propagation through high level primitives (HLPs). Reduced ordered ternary decision diagrams are used to describe HLPs. The technique is implemented in an HTDD fault simulator. The simulator is evaluated with some ITC99 benchmarks. Besides high efficiency (in comparison with existing fault simulators), it shows flexibility for the adoption of a wide range of fault models.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"120 1","pages":"583-586"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79429423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Low power global shutter CMOS active pixel image sensor with ultra-high dynamic range 低功耗全局快门CMOS有源像素图像传感器，具有超高动态范围
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399636
A. Fish, A. Belenky, O. Yadid-Pecht
{"title":"Low power global shutter CMOS active pixel image sensor with ultra-high dynamic range","authors":"A. Fish, A. Belenky, O. Yadid-Pecht","doi":"10.1109/ICECS.2004.1399636","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399636","url":null,"abstract":"A novel low power global shutter CMOS active pixel sensor (APS) with ultra-high dynamic range is presented. Incorporating a sample-and-hold element in each pixel, the sensor enables imaging of fast moving objects in the field of view. An adaptive exposure time is automatically applied to each pixel, according to the local illumination intensity level, significantly increasing the dynamic range of the sensor. Driven by low-power dissipation requirements, the proposed pixel is operated by low voltage supply (1.8V). System architecture and operation are discussed and simulation results in a standard 0.35 /spl mu/m CMOS technology are presented.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"17 1","pages":"149-152"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75150425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique 具有自校准电流偏置技术的10-b 500 MSPS电流转向CMOS D/A转换器
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399666
Sanghoon Hwang, Minkyu Song
{"title":"A 10-b 500 MSPS current-steering CMOS D/A converter with a self-calibrated current biasing technique","authors":"Sanghoon Hwang, Minkyu Song","doi":"10.1109/ICECS.2004.1399666","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399666","url":null,"abstract":"A 10-b 500 MSPS current-steering CMOS digital-to-analog converter with internal termination resistors is presented. In order to improve the device-mismatching problem of internal termination resistors, a self-calibrated current bias circuit is designed. With the self-calibrated current bias circuit, the gain error of the output voltage swing is reduced within 0.5%. Further, for the purpose of reducing glitch noise, a novel current switch based on a deglitching circuit is proposed. A 10-b CMOS DAC has been fabricated with a 3 V, 0.35 /spl mu/m technology, and it consumes 45 mW. The measured SFDR (spurious free dynamic range) is about 65 dB, when the input signal is about 8 MHz at 500 MHz clock frequency.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"24 1","pages":"254-257"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73575890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Criterion of design for small value integrated self-inductors 小值集成自感器设计准则
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399725
G. Petit, R. Kielbasa, V. Petit
{"title":"Criterion of design for small value integrated self-inductors","authors":"G. Petit, R. Kielbasa, V. Petit","doi":"10.1109/ICECS.2004.1399725","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399725","url":null,"abstract":"Facing the increased frequencies used in analog products, integrated-circuit designers find that the X or upper band has its own problems, especially in the case of passive components. The paper focuses on inductor design and layout, opposing classical analog integrated inductors and hyper frequency lines. After studying separately each solution and pointing out their limits on an actual SOS (silicon on sapphire) 0.5 /spl mu/m case, a methodology to solve this issue is revealed and a chosen criterion is supplied.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"68 1","pages":"491-494"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73494385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and design of a dual band reconfigurable VCO 双频可重构压控振荡器的分析与设计
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399608
A. Mazzanti, P. Uggetti, R. Battaglia, F. Svelto
{"title":"Analysis and design of a dual band reconfigurable VCO","authors":"A. Mazzanti, P. Uggetti, R. Battaglia, F. Svelto","doi":"10.1109/ICECS.2004.1399608","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399608","url":null,"abstract":"A systematic approach to the design of reconfigurable LC VCOs is proposed in this paper. The focus is on the choice of the reactive element of the tank most suited to switch the oscillation frequency. The optimum is the component that determines the tank Q. As an example, the design of a GSM900/1800 VCO in a 0.13 /spl mu/m CMOS technology, switching a series inductor, is discussed. At this frequency, the tank Q is roughly the inductor Q, and series inductor switching allows area savings with respect to parallel switching.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"35 1","pages":"37-40"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78336783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits 无输入级联码V/sub thn/和V/sub thp/提取电路
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399673
Yanbin Wang, G. Tarr, Yanjie Wang
{"title":"Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits","authors":"Yanbin Wang, G. Tarr, Yanjie Wang","doi":"10.1109/ICECS.2004.1399673","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399673","url":null,"abstract":"Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"44 1","pages":"282-285"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90852735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of on-chip PLL irregularities under stress conditions - case study 应力条件下片上锁相环不规则性的研究-案例研究
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399750
Y. Weizman, Y. Fefer, S. Sofer, E. Baruch
{"title":"Investigation of on-chip PLL irregularities under stress conditions - case study","authors":"Y. Weizman, Y. Fefer, S. Sofer, E. Baruch","doi":"10.1109/ICECS.2004.1399750","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399750","url":null,"abstract":"In modern high performance VLSI design, on-chip phase locked loop (PLL) performance degradation due to intensive core switching activities is becoming an influential factor. Under certain borderline conditions, the PLL may become unstable. The analysis herein describes PLL irregularities under marginal mode, frequency and voltage conditions combined with intensive core operations. After lengthy analysis that included step-by-step elimination of all noise sources, the cause of instability was explained by coupling between a voltage spike on core power supply line and the internal control signal of the voltage controlled oscillator of the PLL through the chip substrate. The solution to the problem was suggested by changing the PLL dynamic characteristics. Through this investigation we studied the noise crosstalk issue in mixed mode (analog and digital) systems and also the PLL dynamics under stress conditions, which demonstrates the complexity of PLL analysis in a system-on-chip environment.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"1 1","pages":"591-594"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90250412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impedance characteristics of decoupling capacitors in multi-power distribution systems 多配电系统中去耦电容器的阻抗特性
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399639
M. Popovich, E. Friedman
{"title":"Impedance characteristics of decoupling capacitors in multi-power distribution systems","authors":"M. Popovich, E. Friedman","doi":"10.1109/ICECS.2004.1399639","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399639","url":null,"abstract":"To decrease power consumption without affecting circuit speed, multiple power supply voltages are often used in modern high performance IC such as microprocessors. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is the focus of this paper. The dependence of the impedance on the power distribution system parameters is investigated. An antiresonance phenomenon is intuitively explained in this paper. Design techniques to cancel and shift the antiresonant spikes out of range of the operating frequencies are presented.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"66 1","pages":"160-163"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82339157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A high-speed CMOS op-amp design technique using negative Miller capacitance 采用负米勒电容的高速CMOS运算放大器设计技术
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399758
Boaz Shem-Tov, M. Kozak, E. Friedman
{"title":"A high-speed CMOS op-amp design technique using negative Miller capacitance","authors":"Boaz Shem-Tov, M. Kozak, E. Friedman","doi":"10.1109/ICECS.2004.1399758","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399758","url":null,"abstract":"A method is presented in this paper for the design of high speed CMOS operational amplifiers (op-amp). The op-amp consists of an operational transconductance amplifier (OTA) followed by an output buffer. The OTA is compensated with a capacitor connected between the input and output of the buffer. An op-amp is designed in a 0.18 /spl mu/m standard digital CMOS technology and exhibits 86 dB DC gain. The unity gain frequency and phase margin are 392 MHz and 73/spl deg/, respectively, for a parallel combination of 2 pF and 1 k/spl Omega/ load. As compared to the conventional approach, the proposed compensation method results in a 1.5 times increase in unity gain frequency and a 35/spl deg/ improvement in the phase margin under the same load conditions.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"18 1","pages":"623-626"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81510038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
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