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Fast high-level fault simulator 快速高级故障模拟器
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399748
S. Deniziak, K. Sapiecha
{"title":"Fast high-level fault simulator","authors":"S. Deniziak, K. Sapiecha","doi":"10.1109/ICECS.2004.1399748","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399748","url":null,"abstract":"A new fast fault simulation technique is presented for calculating fault propagation through high level primitives (HLPs). Reduced ordered ternary decision diagrams are used to describe HLPs. The technique is implemented in an HTDD fault simulator. The simulator is evaluated with some ITC99 benchmarks. Besides high efficiency (in comparison with existing fault simulators), it shows flexibility for the adoption of a wide range of fault models.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"120 1","pages":"583-586"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79429423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automatic hardware-efficient SoC integration by QoS network on chip 自动硬件高效SoC集成的QoS网络片上
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399722
Evgeny Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny
{"title":"Automatic hardware-efficient SoC integration by QoS network on chip","authors":"Evgeny Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny","doi":"10.1109/ICECS.2004.1399722","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399722","url":null,"abstract":"Efficient module integration in systems on chip (SoC) is a great challenge. We present a novel automated network on chip (NoC) centric integration method for large and complex SoCs. A quality of service NoC (QNoC) architecture and its design considerations are presented. Then, we describe a chain of design automation tools that allows fast and hardware-efficient SoC integration using the QNoC paradigm. The tool-chain receives a list of system modules and their inter-module communication requirements and results in complete system hardware and verification models for faster SoC fabrication and easier verification.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"11 1","pages":"479-482"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84427397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Implementation of the Berlekamp-Massey algorithm using a DSP 使用DSP实现Berlekamp-Massey算法
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399692
S. Greenberg, Nir Feldblum, Gal Melamed
{"title":"Implementation of the Berlekamp-Massey algorithm using a DSP","authors":"S. Greenberg, Nir Feldblum, Gal Melamed","doi":"10.1109/ICECS.2004.1399692","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399692","url":null,"abstract":"Reed-Solomon (RS) codes are error-correcting codes used in many of today's communication systems. RS encoding and decoding are typically implemented using dedicated hardware elements used in ADSL modems and digital TV. In this paper we propose using software in lieu of a hardware-based RS de-coder. This is accomplished using the Berlekamp-Massey algorithm, implemented on a programmable DSP. This software-based RS decoder using Berlekamp-Massey is implemented on Motorola's MSC8101 StarCore DSP. In order to evaluate the algorithm we use the following criteria: computation cost; cycle count, critical paths in the decoding scheme, and error location in the codeword. Furthermore, we examine the effect of changing the RS code's k, t parameters and its primitive polynomial in real-time implementation. The Berlekamp-Massey algorithm operates over finite field arithmetic, whose steps, as applied on the StarCore DSP, are discussed in detail and specifically evaluated using the assembly code for the syndrome search. We conclude that the Berlekamp-Massey algorithm, used for RS decoding, should be implemented using long codewords.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"67 1","pages":"358-361"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90677328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 100 dB CMRR CMOS operational amplifier with single-supply capability 具有单电源能力的100 dB CMRR CMOS运算放大器
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399601
V. Ivanov, Junlin Zhou, I. Filanovsky
{"title":"A 100 dB CMRR CMOS operational amplifier with single-supply capability","authors":"V. Ivanov, Junlin Zhou, I. Filanovsky","doi":"10.1109/ICECS.2004.1399601","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399601","url":null,"abstract":"A CMOS operational amplifier that has a 100 dB CMRR (common mode rejection ratio) is described. This is achieved by combining the high output impedance tail current source with control of the drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail voltage. This is obtained by applying the controlled bulk biasing of both input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors with voltage gain boost. The suppression of impact ionization current in the output stage improves the gain by more than 20 dB.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"287 1","pages":"9-12"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77839438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Criterion of design for small value integrated self-inductors 小值集成自感器设计准则
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399725
G. Petit, R. Kielbasa, V. Petit
{"title":"Criterion of design for small value integrated self-inductors","authors":"G. Petit, R. Kielbasa, V. Petit","doi":"10.1109/ICECS.2004.1399725","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399725","url":null,"abstract":"Facing the increased frequencies used in analog products, integrated-circuit designers find that the X or upper band has its own problems, especially in the case of passive components. The paper focuses on inductor design and layout, opposing classical analog integrated inductors and hyper frequency lines. After studying separately each solution and pointing out their limits on an actual SOS (silicon on sapphire) 0.5 /spl mu/m case, a methodology to solve this issue is revealed and a chosen criterion is supplied.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"68 1","pages":"491-494"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73494385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis and design of a dual band reconfigurable VCO 双频可重构压控振荡器的分析与设计
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399608
A. Mazzanti, P. Uggetti, R. Battaglia, F. Svelto
{"title":"Analysis and design of a dual band reconfigurable VCO","authors":"A. Mazzanti, P. Uggetti, R. Battaglia, F. Svelto","doi":"10.1109/ICECS.2004.1399608","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399608","url":null,"abstract":"A systematic approach to the design of reconfigurable LC VCOs is proposed in this paper. The focus is on the choice of the reactive element of the tank most suited to switch the oscillation frequency. The optimum is the component that determines the tank Q. As an example, the design of a GSM900/1800 VCO in a 0.13 /spl mu/m CMOS technology, switching a series inductor, is discussed. At this frequency, the tank Q is roughly the inductor Q, and series inductor switching allows area savings with respect to parallel switching.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"35 1","pages":"37-40"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78336783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits 无输入级联码V/sub thn/和V/sub thp/提取电路
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399673
Yanbin Wang, G. Tarr, Yanjie Wang
{"title":"Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits","authors":"Yanbin Wang, G. Tarr, Yanjie Wang","doi":"10.1109/ICECS.2004.1399673","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399673","url":null,"abstract":"Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"44 1","pages":"282-285"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90852735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Investigation of on-chip PLL irregularities under stress conditions - case study 应力条件下片上锁相环不规则性的研究-案例研究
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399750
Y. Weizman, Y. Fefer, S. Sofer, E. Baruch
{"title":"Investigation of on-chip PLL irregularities under stress conditions - case study","authors":"Y. Weizman, Y. Fefer, S. Sofer, E. Baruch","doi":"10.1109/ICECS.2004.1399750","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399750","url":null,"abstract":"In modern high performance VLSI design, on-chip phase locked loop (PLL) performance degradation due to intensive core switching activities is becoming an influential factor. Under certain borderline conditions, the PLL may become unstable. The analysis herein describes PLL irregularities under marginal mode, frequency and voltage conditions combined with intensive core operations. After lengthy analysis that included step-by-step elimination of all noise sources, the cause of instability was explained by coupling between a voltage spike on core power supply line and the internal control signal of the voltage controlled oscillator of the PLL through the chip substrate. The solution to the problem was suggested by changing the PLL dynamic characteristics. Through this investigation we studied the noise crosstalk issue in mixed mode (analog and digital) systems and also the PLL dynamics under stress conditions, which demonstrates the complexity of PLL analysis in a system-on-chip environment.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"1 1","pages":"591-594"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90250412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impedance characteristics of decoupling capacitors in multi-power distribution systems 多配电系统中去耦电容器的阻抗特性
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399639
M. Popovich, E. Friedman
{"title":"Impedance characteristics of decoupling capacitors in multi-power distribution systems","authors":"M. Popovich, E. Friedman","doi":"10.1109/ICECS.2004.1399639","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399639","url":null,"abstract":"To decrease power consumption without affecting circuit speed, multiple power supply voltages are often used in modern high performance IC such as microprocessors. To maintain the impedance of a power distribution system below a specified level, multiple decoupling capacitors are placed at different levels of the power grid hierarchy. The system of decoupling capacitors used in power distribution systems with multiple power supplies is the focus of this paper. The dependence of the impedance on the power distribution system parameters is investigated. An antiresonance phenomenon is intuitively explained in this paper. Design techniques to cancel and shift the antiresonant spikes out of range of the operating frequencies are presented.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"66 1","pages":"160-163"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82339157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A high-speed CMOS op-amp design technique using negative Miller capacitance 采用负米勒电容的高速CMOS运算放大器设计技术
Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399758
Boaz Shem-Tov, M. Kozak, E. Friedman
{"title":"A high-speed CMOS op-amp design technique using negative Miller capacitance","authors":"Boaz Shem-Tov, M. Kozak, E. Friedman","doi":"10.1109/ICECS.2004.1399758","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399758","url":null,"abstract":"A method is presented in this paper for the design of high speed CMOS operational amplifiers (op-amp). The op-amp consists of an operational transconductance amplifier (OTA) followed by an output buffer. The OTA is compensated with a capacitor connected between the input and output of the buffer. An op-amp is designed in a 0.18 /spl mu/m standard digital CMOS technology and exhibits 86 dB DC gain. The unity gain frequency and phase margin are 392 MHz and 73/spl deg/, respectively, for a parallel combination of 2 pF and 1 k/spl Omega/ load. As compared to the conventional approach, the proposed compensation method results in a 1.5 times increase in unity gain frequency and a 35/spl deg/ improvement in the phase margin under the same load conditions.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":"18 1","pages":"623-626"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81510038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
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