Input-free cascode V/sub thn/ and V/sub thp/ extractor circuits

Abstract

Input-free nMOS and pMOS V/sub th/ (threshold voltage) extractor circuits are presented. They use a cascode structure to eliminate the error caused by the body effect. The extracted V/sub th/ for nMOS and pMOS is referenced to ground and V/sub DD/ respectively. Both nMOS and pMOS V/sub th/ extractors have high accuracy of almost 100% from the HSPICE simulation. The nMOS and pMOS extractor circuits have been simulated in HSPICE using TSMC 0.35 /spl mu/m CMOS technology at 2 V and 2.9 V power supply with low power consumption of 0.29 mW and 0.44 mW respectively.