Giornale di Storia Costituzionale最新文献_第10页

Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing 芯片级时钟树性能的优化使用同步驱动和线尺寸

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399707

S. Greenberg, Ido Bloch, M. Horwitz, A. Maman

{"title":"Optimization of chip level clock tree performance by using simultaneous drivers and wire sizing","authors":"S. Greenberg, Ido Bloch, M. Horwitz, A. Maman","doi":"10.1109/ICECS.2004.1399707","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399707","url":null,"abstract":"Defining the optimal clock-distribution network in VLSI is one of the most important aspects of high-speed SoC design. The existing design flows for clock tree network implementation are manual based and require long development cycle time. This long and iterative design flow is not optimized in terms of: clock-skew, insertion delay, clock signal rise/fall time, power dissipation, route resources, sensitivity to technology/design variations and time to market. This paper demonstrates a new approach which uses preliminary HSPICE simulations and dramatically improves the clock tree performance. This is done by smartly choosing the following parameters: number of driver levels, driver size, wire width/space and wire length between levels. These parameters are used as inputs to an automatic clock tree synthesis tool in order to get better results by the automatic synthesis tool. This approach is applied to a chip level clock tree network of the new Freescale Semiconductor MSC8122 Quad Core DSP (500 MHz, 90 nm CMOS technology, 0.9686 cm/spl times/1.1792 cm die size). This results in saving 12% power dissipation and 15% route area without performance decreasing compared to the manual based flow.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85824102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Analysis of the probability distribution of the baseline wander effect for baseband PAM transmission with application to gigabit Ethernet 基带PAM传输基线漂移效应的概率分布分析及其在千兆以太网中的应用

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399621

N. Sommer, Itay Lusky, M. Miller

{"title":"Analysis of the probability distribution of the baseline wander effect for baseband PAM transmission with application to gigabit Ethernet","authors":"N. Sommer, Itay Lusky, M. Miller","doi":"10.1109/ICECS.2004.1399621","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399621","url":null,"abstract":"Communication systems that employ baseband transmission (i.e. signal spectrum centered around 0 Hz) may suffer from the baseline wander (BLW) phenomenon. This phenomenon occurs when the signal has to pass through a highpass filter element in the transmission path (e.g. a transformer in the line interface). A long sequence of symbols with constant value should generate a signal with constant level, but the signal will decay towards zero due to the highpass element. An example of a communication standard where baseband transmission is used with a DC-coupled channel is Ethernet. It can be shown that for baseband pulse amplitude modulation (PAM), the baseline wander phenomenon increases the dynamic range of the signal by a factor of 2, in worst case. This increases the cost of the receiver (for example, another bit may be needed in the analog to digital converter). However, the signal will reach its extreme values with very low probability, so it seems wasteful to design for worst case. It may be more economical to design for a smaller dynamic range, but then there must be a way to understand the probability that the signal will exceed this range. This can be done by using the probability distribution of the signal in the presence of BLW, which is calculated approximately in this paper.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88919134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Towards a spiking VLSI implementation of Freeman's olfactory model 迈向Freeman嗅觉模型的峰值VLSI实现

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399649

T. A. Holz, J. Harris

引用次数: 0

Evaluating and comparing simulation verification vs. formal verification approach on block level design 评估和比较块级设计的仿真验证与形式验证方法

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399731

Eyal Segev, Sharon Goldshlager, H. Miller, Oren Shua, Olga Sher, S. Greenberg

{"title":"Evaluating and comparing simulation verification vs. formal verification approach on block level design","authors":"Eyal Segev, Sharon Goldshlager, H. Miller, Oren Shua, Olga Sher, S. Greenberg","doi":"10.1109/ICECS.2004.1399731","DOIUrl":"https://doi.org/10.1109/ICECS.2004.1399731","url":null,"abstract":"Logic design has become very complex in term of logic functionality. System-on-chip (SOC) designs are an integration of multiple modules and cores. In many cases, SOC integration is a result of integrating a few chips together. Each piece (module or core) must be verified separately (stand alone) prior to chip level verification. Standalone logic verification of the design is one of the most important steps in the overall design effort. Following the increase of the amount of functionality at each module, the logic verification effort has become a very resource-consuming task. Two logic verification methods are commonly used when verifying a SOC, simulation based verification and formal based verification. The two methods are explored and compared with respect to the time required for setup and running the environment, ease of debugging the reported failures, power, coverage and confidence level. Our main goal is to establish criteria for optimal use of simulation based verification and formal based verification and implement both methods on a block for a PCMCIA interface card. We have derived important conclusions concerning the matching of these methods for the verification of blocks of a similar type.","PeriodicalId":38467,"journal":{"name":"Giornale di Storia Costituzionale","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74034627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

New chaotic third-order log-domain oscillator with tanh nonlinearity 新型tanh非线性混沌三阶对数域振荡器

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399618

A. Ascoli, P. Curran, O. Feely

引用次数: 3

Controlling an electrical motion system by a load instruction decoding algorithm using FPGA 基于FPGA的负载指令解码算法控制电动运动系统

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399713

Simon R. Cooper, A. Kuperman, R. Rabinovici

引用次数: 1

A novel design and fabrication method of a pyramidal shape chip for scanning micro mirror 一种新型扫描微镜锥体芯片的设计与制造方法

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399720

O. Cohen, A. Shai, Y. Nemirovsky

引用次数: 2

Computer aided design using CGH of a three-dimensional objects 利用计算机辅助CGH设计一个三维物体

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399737

D. Abookasis, Joseph Rosen

引用次数: 1

Differential tuning oscillators with reduced flicker noise upconversion 具有减少闪烁噪声上转换的差分调谐振荡器

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399607

S. Levantino, A. Bonfanti, L. Romanò, C. Samori, A. Lacaita

引用次数: 1

Sparse approximations with a high resolution greedy algorithm 稀疏逼近与高分辨率贪婪算法

Giornale di Storia Costituzionale Pub Date : 2004-12-13 DOI: 10.1109/ICECS.2004.1399685

B. G. Salomon, H. Ur

引用次数: 2